diff options
| -rw-r--r-- | techlibs/greenpak4/cells_sim_digital.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index eb18a20b6..fc481975c 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -86,7 +86,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT); end "LEVEL": begin - always @(posedge CLK or RST) begin + always @(posedge CLK or posedge RST) begin count <= count - 1'd1; if(count == 0) count <= COUNT_TO; @@ -204,7 +204,7 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, end "LEVEL": begin - always @(posedge CLK or RST) begin + always @(posedge CLK or posedge RST) begin //Main counter if(KEEP) begin @@ -339,7 +339,7 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, end "LEVEL": begin - always @(posedge CLK or RST) begin + always @(posedge CLK or posedge RST) begin //Main counter if(KEEP) begin @@ -439,7 +439,7 @@ module GP_COUNT8( end "LEVEL": begin - always @(posedge CLK or RST) begin + always @(posedge CLK or posedge RST) begin count <= count - 1'd1; if(count == 0) count <= COUNT_TO; |