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-rw-r--r--kernel/register.cc34
-rw-r--r--kernel/register.h7
-rw-r--r--passes/hierarchy/submod.cc2
-rw-r--r--passes/techmap/techmap.cc10
4 files changed, 37 insertions, 16 deletions
diff --git a/kernel/register.cc b/kernel/register.cc
index 8da5a725f..84051948f 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -198,11 +198,11 @@ void Pass::call(RTLIL::Design *design, std::vector<std::string> args)
design->check();
}
-void Pass::call_newsel(RTLIL::Design *design, std::string command)
+void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)
{
std::string backup_selected_active_module = design->selected_active_module;
design->selected_active_module.clear();
- design->selection_stack.push_back(RTLIL::Selection());
+ design->selection_stack.push_back(selection);
Pass::call(design, command);
@@ -210,11 +210,37 @@ void Pass::call_newsel(RTLIL::Design *design, std::string command)
design->selected_active_module = backup_selected_active_module;
}
-void Pass::call_newsel(RTLIL::Design *design, std::vector<std::string> args)
+void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::vector<std::string> args)
{
std::string backup_selected_active_module = design->selected_active_module;
design->selected_active_module.clear();
- design->selection_stack.push_back(RTLIL::Selection());
+ design->selection_stack.push_back(selection);
+
+ Pass::call(design, args);
+
+ design->selection_stack.pop_back();
+ design->selected_active_module = backup_selected_active_module;
+}
+
+void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command)
+{
+ std::string backup_selected_active_module = design->selected_active_module;
+ design->selected_active_module = module->name;
+ design->selection_stack.push_back(RTLIL::Selection(false));
+ design->selection_stack.back().select(module);
+
+ Pass::call(design, command);
+
+ design->selection_stack.pop_back();
+ design->selected_active_module = backup_selected_active_module;
+}
+
+void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args)
+{
+ std::string backup_selected_active_module = design->selected_active_module;
+ design->selected_active_module = module->name;
+ design->selection_stack.push_back(RTLIL::Selection(false));
+ design->selection_stack.back().select(module);
Pass::call(design, args);
diff --git a/kernel/register.h b/kernel/register.h
index f3d3f70ae..b07c46177 100644
--- a/kernel/register.h
+++ b/kernel/register.h
@@ -60,8 +60,11 @@ struct Pass
static void call(RTLIL::Design *design, std::string command);
static void call(RTLIL::Design *design, std::vector<std::string> args);
- static void call_newsel(RTLIL::Design *design, std::string command);
- static void call_newsel(RTLIL::Design *design, std::vector<std::string> args);
+ static void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command);
+ static void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::vector<std::string> args);
+
+ static void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command);
+ static void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args);
static void init_register();
static void done_register();
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 7d0811254..55f5f0485 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -338,7 +338,7 @@ struct SubmodPass : public Pass {
if (module == NULL)
log("Nothing selected -> do nothing.\n");
else {
- Pass::call_newsel(design, stringf("opt_clean %s", module->name.c_str()));
+ Pass::call_on_module(design, module, "opt_clean");
log_header("Continuing SUBMOD pass.\n");
SubmodWorker worker(design, module, opt_name);
}
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index cb36c9e1f..3ceff279b 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -393,15 +393,7 @@ struct TechmapWorker
tpl->add(data.wire);
std::string cmd_string = data.value.as_const().decode_string();
-
- RTLIL::Selection tpl_mod_sel(false);
- std::string backup_active_module = map->selected_active_module;
- map->selected_active_module = tpl->name;
- tpl_mod_sel.select(tpl);
- map->selection_stack.push_back(tpl_mod_sel);
- Pass::call(map, cmd_string);
- map->selection_stack.pop_back();
- map->selected_active_module = backup_active_module;
+ Pass::call_on_module(map, tpl, cmd_string);
keep_running = true;
break;