diff options
| -rw-r--r-- | kernel/celltypes.h | 9 | ||||
| -rw-r--r-- | kernel/sigtools.h | 24 |
2 files changed, 33 insertions, 0 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 6273e926a..bf5ef4b38 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -29,6 +29,15 @@ struct CellTypes std::set<std::string> cell_types; std::vector<const RTLIL::Design*> designs; + CellTypes() + { + } + + CellTypes(const RTLIL::Design *design) + { + setup(design); + } + void setup(const RTLIL::Design *design = NULL) { if (design) diff --git a/kernel/sigtools.h b/kernel/sigtools.h index e6c09331d..f081957c7 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -164,6 +164,18 @@ struct SigSet } } + void insert(RTLIL::SigSpec sig, const std::set<T> &data) + { + sig.expand(); + for (auto &c : sig.chunks) { + if (c.wire == NULL) + continue; + assert(c.width == 1); + bitDef_t bit(c.wire, c.offset); + bits[bit].insert(data.begin(), data.end()); + } + } + void erase(RTLIL::SigSpec sig) { sig.expand(); @@ -188,6 +200,18 @@ struct SigSet } } + void erase(RTLIL::SigSpec sig, const std::set<T> &data) + { + sig.expand(); + for (auto &c : sig.chunks) { + if (c.wire == NULL) + continue; + assert(c.width == 1); + bitDef_t bit(c.wire, c.offset); + bits[bit].erase(data.begin(), data.end()); + } + } + void find(RTLIL::SigSpec sig, std::set<T> &result) { sig.expand(); |