diff options
| -rw-r--r-- | techlibs/machxo2/cells_map.v | 2 | ||||
| -rw-r--r-- | tests/arch/machxo2/dffs.ys | 10 |
2 files changed, 11 insertions, 1 deletions
diff --git a/techlibs/machxo2/cells_map.v b/techlibs/machxo2/cells_map.v index 345675db9..054b678b3 100644 --- a/techlibs/machxo2/cells_map.v +++ b/techlibs/machxo2/cells_map.v @@ -24,4 +24,4 @@ module \$lut (A, Y); LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .F(Y)); endmodule -module \$_DFF_P_ (input D, C, output Q); FACADE_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .D(D), .Q(Q)); endmodule +module \$_DFF_P_ (input D, C, output Q); FACADE_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule diff --git a/tests/arch/machxo2/dffs.ys b/tests/arch/machxo2/dffs.ys new file mode 100644 index 000000000..3e9f87fec --- /dev/null +++ b/tests/arch/machxo2/dffs.ys @@ -0,0 +1,10 @@ +read_verilog ../common/dffs.v +design -save read + +hierarchy -top dff +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:FACADE_FF +select -assert-none t:FACADE_FF %% t:* %D |