diff options
| -rw-r--r-- | techlibs/common/Makefile.inc | 1 | ||||
| -rw-r--r-- | techlibs/common/shiftx2mux.v | 38 | ||||
| -rw-r--r-- | tests/techmap/shiftx2mux.ys | 110 |
3 files changed, 149 insertions, 0 deletions
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index a42f63128..5d797ec1d 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -30,3 +30,4 @@ $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v)) $(eval $(call add_share_file,share,techlibs/common/cells.lib)) $(eval $(call add_share_file,share,techlibs/common/mul2dsp.v)) $(eval $(call add_share_file,share,techlibs/common/dummy.box)) +$(eval $(call add_share_file,share,techlibs/common/shiftx2mux.v)) diff --git a/techlibs/common/shiftx2mux.v b/techlibs/common/shiftx2mux.v new file mode 100644 index 000000000..5366d6749 --- /dev/null +++ b/techlibs/common/shiftx2mux.v @@ -0,0 +1,38 @@ +(* techmap_celltype = /*"$shift*/ "$shiftx" *) +module _80_shift_shiftx (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; + parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; + + generate + genvar i; + localparam CLOG2_Y_WIDTH = $clog2(Y_WIDTH); + + if (B_WIDTH <= CLOG2_Y_WIDTH+1) + wire _TECHMAP_FAIL_ = 1; + // In order to perform this optimisation, this $shiftx must + // only shift in units of Y_WIDTH, which we check by ensuring + // that the appropriate LSBs of B are zero + else if (_TECHMAP_CONSTMSK_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b1}} && _TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] != {CLOG2_Y_WIDTH{1'b0}}) + wire _TECHMAP_FAIL_ = 1; + else begin + // Halve the size of $shiftx by $mux-ing A according to + // the LSB of B, after discarding the zeroed bits + wire [(A_WIDTH+Y_WIDTH)/2-1:0] AA; + for (i = 0; i < (A_WIDTH/Y_WIDTH); i=i+2) + assign AA[(i/2)*Y_WIDTH +: Y_WIDTH] = B[CLOG2_Y_WIDTH] ? A[(i+1)*Y_WIDTH +: Y_WIDTH] : A[(i+0)*Y_WIDTH +: Y_WIDTH]; + $shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+Y_WIDTH)/2'd2), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B({B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}}), .Y(Y)); + end + endgenerate +endmodule + + diff --git a/tests/techmap/shiftx2mux.ys b/tests/techmap/shiftx2mux.ys new file mode 100644 index 000000000..acdd54e9e --- /dev/null +++ b/tests/techmap/shiftx2mux.ys @@ -0,0 +1,110 @@ +read_verilog <<EOT +module sc1 (i1 , + i2 , + i3 , + i4 , + i5 , + i6 , + i7 , + i8 , + i9 , + i10, + i11, + i12, + i13, + i14, + i15, + binary_out, + encoder_in, + enable +); + +input [3:0] i1 ; +input [3:0] i2 ; +input [3:0] i3 ; +input [3:0] i4 ; +input [3:0] i5 ; +input [3:0] i6 ; +input [3:0] i7 ; +input [3:0] i8 ; +input [3:0] i9 ; +input [3:0] i10 ; +input [3:0] i11 ; +input [3:0] i12 ; +input [3:0] i13 ; +input [3:0] i14 ; +input [3:0] i15 ; + +output reg [3:0] binary_out ; + +input [3:0] encoder_in ; +input enable ; + + + +always @ (*) +begin + binary_out = 0; + if (enable) begin + case (encoder_in) + 4'h1 : binary_out = i1; + 4'h2 : binary_out = i2; + 4'h3 : binary_out = i3; + 4'h4 : binary_out = i4; + 4'h5 : binary_out = i5; + 4'h6 : binary_out = i6; + 4'h7 : binary_out = i7; + 4'h8 : binary_out = i8; + 4'h9 : binary_out = i9; + 4'ha : binary_out = i10; + 4'hb : binary_out = i11;/* + 4'hc : binary_out = i12; + 4'hd : binary_out = i13; + 4'he : binary_out = i14; + 4'hf : binary_out = i15;*/ + endcase + end +end +endmodule +EOT + +proc +pmux2shiftx +design -save gold + + +design -load gold +techmap +abc -lut 6 +select -assert-min 17 t:$lut + + +design -load gold +techmap -map +/shiftx2mux.v -map +/techmap.v +abc -lut 6 +select -assert-count 16 t:$lut + +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + + +design -load gold +techmap +abc9 -lut 6 +select -assert-min 17 t:$lut + + +design -load gold +techmap -map +/shiftx2mux.v -map +/techmap.v +abc9 -lut 6 +select -assert-count 16 t:$lut + +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + |