diff options
| -rw-r--r-- | passes/sat/sim.cc | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index b7085369a..75f922dba 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -22,6 +22,8 @@ #include "kernel/celltypes.h" #include "kernel/mem.h" +#include <ctime> + USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -620,6 +622,7 @@ struct SimWorker : SimShared SimInstance *top = nullptr; std::ofstream vcdfile; pool<IdString> clock, clockn, reset, resetn; + std::string timescale; ~SimWorker() { @@ -631,6 +634,17 @@ struct SimWorker : SimShared if (!vcdfile.is_open()) return; + vcdfile << stringf("$version %s $end\n", yosys_version_str); + + std::time_t t = std::time(nullptr); + char mbstr[255]; + if (std::strftime(mbstr, sizeof(mbstr), "%c", std::localtime(&t))) { + vcdfile << stringf("$date ") << mbstr << stringf(" $end\n"); + } + + if (!timescale.empty()) + vcdfile << stringf("$timescale %s $end\n", timescale.c_str()); + int id = 1; top->write_vcd_header(vcdfile, id); @@ -770,6 +784,9 @@ struct SimPass : public Pass { log(" -zinit\n"); log(" zero-initialize all uninitialized regs and memories\n"); log("\n"); + log(" -timescale <string>\n"); + log(" include the specified timescale declaration in the vcd\n"); + log("\n"); log(" -n <integer>\n"); log(" number of cycles to simulate (default: 20)\n"); log("\n"); @@ -820,6 +837,10 @@ struct SimPass : public Pass { worker.resetn.insert(RTLIL::escape_id(args[++argidx])); continue; } + if (args[argidx] == "-timescale" && argidx+1 < args.size()) { + worker.timescale = args[++argidx]; + continue; + } if (args[argidx] == "-a") { worker.hide_internal = false; continue; |