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author | Eddie Hung <eddie@fpgeh.com> | 2020-01-12 15:19:41 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-12 15:19:41 -0800 |
commit | f9aae90e7a9d238f5063d980e2b1e85a94cff4c7 (patch) | |
tree | 90cdb2422cf1194b6ab72997a82c54e5e0b4818c /tests | |
parent | f24de88f385a3eeaadd9b9c8c200a7c338f37448 (diff) | |
parent | 295e241c074ae275e832fdde9fae6fd897170ac8 (diff) | |
download | yosys-f9aae90e7a9d238f5063d980e2b1e85a94cff4c7.tar.gz yosys-f9aae90e7a9d238f5063d980e2b1e85a94cff4c7.tar.bz2 yosys-f9aae90e7a9d238f5063d980e2b1e85a94cff4c7.zip |
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
Diffstat (limited to 'tests')
-rw-r--r-- | tests/arch/ecp5/bug1459.ys | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/tests/arch/ecp5/bug1459.ys b/tests/arch/ecp5/bug1459.ys new file mode 100644 index 000000000..1142ae0b5 --- /dev/null +++ b/tests/arch/ecp5/bug1459.ys @@ -0,0 +1,25 @@ +read_verilog <<EOT +module register_file( + input wire clk, + input wire write_enable, + input wire [63:0] write_data, + input wire [4:0] write_reg, + input wire [4:0] read1_reg, + output reg [63:0] read1_data, + ); + + reg [63:0] registers[0:31]; + + always @(posedge clk) begin + if (write_enable == 1'b1) begin + registers[write_reg] <= write_data; + end + end + + always @(all) begin + read1_data <= registers[read1_reg]; + end +endmodule +EOT + +synth_ecp5 -abc9 |