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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-01 16:26:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-01 16:26:43 -0700 |
| commit | f86d153cef724af9d30e4139783a7e14d7ba0a19 (patch) | |
| tree | 1c2cd09407cbeef2f68c19f9bcfb95566355fa01 /tests | |
| parent | acafcdc94dc148b2bf9c8faef173e5b2b54e1ac5 (diff) | |
| parent | 7a0af004a0a4dc3831997f0845d40fc3ea514281 (diff) | |
| download | yosys-f86d153cef724af9d30e4139783a7e14d7ba0a19.tar.gz yosys-f86d153cef724af9d30e4139783a7e14d7ba0a19.tar.bz2 yosys-f86d153cef724af9d30e4139783a7e14d7ba0a19.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/memories/firrtl_938.v | 22 | ||||
| -rw-r--r-- | tests/simple/xfirrtl | 1 |
2 files changed, 23 insertions, 0 deletions
diff --git a/tests/memories/firrtl_938.v b/tests/memories/firrtl_938.v new file mode 100644 index 000000000..af5efcd25 --- /dev/null +++ b/tests/memories/firrtl_938.v @@ -0,0 +1,22 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end + +endmodule diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl index 50d693513..ba61a4476 100644 --- a/tests/simple/xfirrtl +++ b/tests/simple/xfirrtl @@ -16,6 +16,7 @@ operators.v $pow partsel.v drops modules process.v drops modules realexpr.v drops modules +retime.v Initial value (11110101) for (retime_test.ff) not supported scopes.v original verilog issues ( -x where x isn't declared signed) sincos.v $adff specify.v no code (empty module generates error |