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authorClifford Wolf <clifford@clifford.at>2019-05-28 15:45:15 +0200
committerClifford Wolf <clifford@clifford.at>2019-05-28 15:45:15 +0200
commiteaae0adf57f5f9328feeb0d2954a90abdbe38271 (patch)
tree22f84628e25cc0fb5e1432cb4548d49a3436aef3 /tests
parent2a11c48782d31cd6f9c181f7ff52984cc2ae0351 (diff)
parent816082d5a11e758b6ff68a2dc442fc2519356669 (diff)
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Merge branch 'wandwor' of https://github.com/thasti/yosys into clifford/wandwor
Diffstat (limited to 'tests')
-rw-r--r--tests/various/wandwor.v33
1 files changed, 33 insertions, 0 deletions
diff --git a/tests/various/wandwor.v b/tests/various/wandwor.v
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+module a(Q);
+ output wire Q = 0;
+endmodule
+
+module b(D);
+ input wire D;
+endmodule
+
+module c;
+ // net definitions
+ wor D;
+ wand E;
+
+ // assignments to wired logic nets
+ assign D = 1;
+ assign D = 0;
+ assign D = 1;
+ assign D = 0;
+
+ // assignments of wired logic nets to wires
+ wire F = E;
+
+ genvar i;
+ for (i = 0; i < 3; i = i + 1)
+ begin : genloop
+ // connection of module outputs
+ a a_inst (.Q(E));
+
+ // connection of module inputs
+ b b_inst (.D(E));
+ end
+endmodule
+