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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 09:52:47 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-23 21:36:59 +0200 |
| commit | e807e88b607834170692f56a5538b89fd4175a36 (patch) | |
| tree | 9b94e7a27334a7be697146f9ff6702e81b58fd73 /tests | |
| parent | 846eb5ea98594daed7bf80a3e9c077a1ce7cf6f2 (diff) | |
| download | yosys-e807e88b607834170692f56a5538b89fd4175a36.tar.gz yosys-e807e88b607834170692f56a5538b89fd4175a36.tar.bz2 yosys-e807e88b607834170692f56a5538b89fd4175a36.zip | |
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'tests')
0 files changed, 0 insertions, 0 deletions