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| author | Clifford Wolf <clifford@clifford.at> | 2013-04-13 21:19:10 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-04-13 21:19:10 +0200 |
| commit | e0c408cb4a9fb411aff087d5c1e8c610d3f5bc3d (patch) | |
| tree | 034935880a2713f77256c168a8e37cd0382e33bc /tests | |
| parent | c6198ea5a833008789ecbc9cc4da3ab61fcf4e82 (diff) | |
| download | yosys-e0c408cb4a9fb411aff087d5c1e8c610d3f5bc3d.tar.gz yosys-e0c408cb4a9fb411aff087d5c1e8c610d3f5bc3d.tar.bz2 yosys-e0c408cb4a9fb411aff087d5c1e8c610d3f5bc3d.zip | |
Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/simple/process.v | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/tests/simple/process.v b/tests/simple/process.v index 532586649..8cb4c870e 100644 --- a/tests/simple/process.v +++ b/tests/simple/process.v @@ -1,4 +1,23 @@ +module blocking_cond (in, out); + +input in; +output reg out; +reg tmp; + +always @* begin + tmp = 1; + out = 1'b0; + case (1'b1) + tmp: out = in; + endcase + tmp = 0; +end + +endmodule + +// ------------------------------------------------------------- + module uut(clk, arst, a, b, c, d, e, f, out1); input clk, arst, a, b, c, d, e, f; |