quicklogic: ABC9 synthesis

6 files changed, 17 insertions, 17 deletions

diff --git a/tests/arch/quicklogic/add_sub.ys b/tests/arch/quicklogic/add_sub.ys
index 168b3f8b3..73ee5cb44 100644
--- a/tests/arch/quicklogic/add_sub.ys
+++ b/tests/arch/quicklogic/add_sub.ys
@@ -3,9 +3,9 @@ hierarchy -top top
 equiv_opt -assert -map +/quicklogic/lut_sim.v -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 3 t:LUT2
-select -assert-count 4 t:LUT3
-select -assert-count 4 t:LUT4
+select -assert-count 2 t:LUT2
+select -assert-count 8 t:LUT3
+select -assert-count 2 t:LUT4
 select -assert-count 8 t:inpad
 select -assert-count 8 t:outpad
 select -assert-none t:LUT2 t:LUT3 t:LUT4 t:inpad t:outpad %% t:* %D
diff --git a/tests/arch/quicklogic/counter.ys b/tests/arch/quicklogic/counter.ys
index 0c04b5742..2e266417c 100644
--- a/tests/arch/quicklogic/counter.ys
+++ b/tests/arch/quicklogic/counter.ys
@@ -6,9 +6,9 @@ equiv_opt -assert -multiclock -map +/quicklogic/pp3_cells_sim.v -map +/quicklogi
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT1
-select -assert-count 5 t:LUT2
-select -assert-count 2 t:LUT3
-select -assert-count 3 t:LUT4
+select -assert-count 3 t:LUT2
+select -assert-count 5 t:LUT3
+select -assert-count 1 t:LUT4
 select -assert-count 8 t:dffepc
 select -assert-count 1 t:logic_0
 select -assert-count 1 t:logic_1
diff --git a/tests/arch/quicklogic/fsm.ys b/tests/arch/quicklogic/fsm.ys
index 7ed36b9e4..130dacf42 100644
--- a/tests/arch/quicklogic/fsm.ys
+++ b/tests/arch/quicklogic/fsm.ys
@@ -11,14 +11,13 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd fsm # Constrain all select calls below inside the top module
 
-select -assert-count 3 t:LUT2
-select -assert-count 6 t:LUT3
-select -assert-count 7 t:LUT4
-select -assert-count 6 t:dffepc
+select -assert-count 1 t:LUT2
+select -assert-count 9 t:LUT3
+select -assert-count 4 t:dffepc
 select -assert-count 1 t:logic_0
 select -assert-count 1 t:logic_1
 select -assert-count 3 t:inpad
 select -assert-count 2 t:outpad
 select -assert-count 1 t:ckpad
 
-select -assert-none t:LUT2 t:LUT3 t:LUT4 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
+select -assert-none t:LUT2 t:LUT3 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
diff --git a/tests/arch/quicklogic/latches.ys b/tests/arch/quicklogic/latches.ys
index d7652f749..bcef42990 100644
--- a/tests/arch/quicklogic/latches.ys
+++ b/tests/arch/quicklogic/latches.ys
@@ -32,8 +32,9 @@ proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
 synth_quicklogic
 cd latchsr # Constrain all select calls below inside the top module
-select -assert-count 2 t:LUT3
+select -assert-count 1 t:LUT2
+select -assert-count 1 t:LUT4
 select -assert-count 5 t:inpad
 select -assert-count 1 t:outpad
 
-select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
+select -assert-none t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D
diff --git a/tests/arch/quicklogic/logic.ys b/tests/arch/quicklogic/logic.ys
index 65f48a42b..4b327c00a 100644
--- a/tests/arch/quicklogic/logic.ys
+++ b/tests/arch/quicklogic/logic.ys
@@ -7,8 +7,8 @@ cd top # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:LUT1
 select -assert-count 6 t:LUT2
-select -assert-count 2 t:LUT4
+select -assert-count 2 t:LUT3
 select -assert-count 8 t:inpad
 select -assert-count 10 t:outpad
 
-select -assert-none t:LUT1 t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D
+select -assert-none t:LUT1 t:LUT2 t:LUT3 t:inpad t:outpad %% t:* %D
diff --git a/tests/arch/quicklogic/mux.ys b/tests/arch/quicklogic/mux.ys
index 632d14687..ea17fa99b 100644
--- a/tests/arch/quicklogic/mux.ys
+++ b/tests/arch/quicklogic/mux.ys
@@ -30,13 +30,13 @@ proc
 equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 4 t:LUT2
+select -assert-count 1 t:LUT1
 select -assert-count 1 t:LUT3
 select -assert-count 2 t:mux4x0
 select -assert-count 11 t:inpad
 select -assert-count 1 t:outpad
 
-select -assert-none t:LUT2 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D
+select -assert-none t:LUT1 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D
 
 design -load read
 hierarchy -top mux16