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| author | Clifford Wolf <clifford@clifford.at> | 2017-09-29 11:56:43 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-09-29 11:56:43 +0200 |
| commit | dbfd8460a9f1d24d1c8893dfae7dd272d17a7b6f (patch) | |
| tree | 7afbacc238f153323f425f39987e0520e0b844ee /tests | |
| parent | 637a02eb5cf8ef09a7fb02af31d6149a31460d0f (diff) | |
| download | yosys-dbfd8460a9f1d24d1c8893dfae7dd272d17a7b6f.tar.gz yosys-dbfd8460a9f1d24d1c8893dfae7dd272d17a7b6f.tar.bz2 yosys-dbfd8460a9f1d24d1c8893dfae7dd272d17a7b6f.zip | |
Allow $size and $bits in verilog mode, actually check test case
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/sat/sizebits.sv (renamed from tests/simple/functions01.sv) | 0 | ||||
| -rw-r--r-- | tests/sat/sizebits.ys | 2 |
2 files changed, 2 insertions, 0 deletions
diff --git a/tests/simple/functions01.sv b/tests/sat/sizebits.sv index d7ce2326e..d7ce2326e 100644 --- a/tests/simple/functions01.sv +++ b/tests/sat/sizebits.sv diff --git a/tests/sat/sizebits.ys b/tests/sat/sizebits.ys new file mode 100644 index 000000000..689227a41 --- /dev/null +++ b/tests/sat/sizebits.ys @@ -0,0 +1,2 @@ +read_verilog -sv sizebits.sv +prep; sat -verify -prove-asserts |