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| author | David Shah <dave@ds0.me> | 2020-03-21 17:35:27 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-21 17:35:27 +0000 |
| commit | beab15b77c2b279e6ebd7996d543e28334f5da20 (patch) | |
| tree | 71947fc61b63423bb7a0b6f6cf759c20f5a54fee /tests | |
| parent | f22f2000bda87847a4a28d945f1508733bf285f7 (diff) | |
| parent | fa77fb857b42b32f3d518da8a590c406ddc8eee9 (diff) | |
| download | yosys-beab15b77c2b279e6ebd7996d543e28334f5da20.tar.gz yosys-beab15b77c2b279e6ebd7996d543e28334f5da20.tar.bz2 yosys-beab15b77c2b279e6ebd7996d543e28334f5da20.zip | |
Merge pull request #1794 from YosysHQ/dave/mince-abc9-fix
ice40: Map unmapped 'mince' DFFs to gate level
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/ice40_mince_abc9.ys | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/tests/various/ice40_mince_abc9.ys b/tests/various/ice40_mince_abc9.ys new file mode 100644 index 000000000..408e16f05 --- /dev/null +++ b/tests/various/ice40_mince_abc9.ys @@ -0,0 +1,17 @@ +read_verilog <<EOT + +module top(input clk, ce, input [2:0] a, b, output reg [2:0] q); + + reg [2:0] aa, bb; + + always @(posedge clk) begin + if (ce) begin + aa <= a; + end + bb <= b; + q <= aa + bb; + end +endmodule +EOT + +synth_ice40 -abc9 -dffe_min_ce_use 4 |