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| author | clairexen <claire@symbioticeda.com> | 2020-09-17 18:21:53 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-09-17 18:21:53 +0200 |
| commit | 9e937961dc026751f8961dfff12aa50411750070 (patch) | |
| tree | 4130d805accae2d2505ae0e626082ce7f2c1c6f0 /tests | |
| parent | 859e52af59e75689f7b0615899bc3356ba5a7ca1 (diff) | |
| parent | daee2d967f5785c83123a1afa5b8bdcddf3da1d8 (diff) | |
| download | yosys-9e937961dc026751f8961dfff12aa50411750070.tar.gz yosys-9e937961dc026751f8961dfff12aa50411750070.tar.bz2 yosys-9e937961dc026751f8961dfff12aa50411750070.zip | |
Merge pull request #2330 from antmicro/arrays-fix-multirange-access
Fix unsupported subarray access detection
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/svtypes/multirange_subarray_access.ys | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/svtypes/multirange_subarray_access.ys b/tests/svtypes/multirange_subarray_access.ys new file mode 100644 index 000000000..de57d1423 --- /dev/null +++ b/tests/svtypes/multirange_subarray_access.ys @@ -0,0 +1,12 @@ +logger -expect error "Insufficient number of array indices for a." 1 +read_verilog -sv <<EOT +module foo; +logic a [6:0][4:0][1:0]; +logic b [1:0]; + +assign a[0][0][0] = 1'b0; +assign a[0][0][1] = 1'b1; +assign b = a[0][0]; + +endmodule +EOT |