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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2018-12-28 08:24:31 -0800 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-12-29 12:46:54 +0100 |
| commit | 99706b3bf48de121e58b76d4341d601f0bcc26cd (patch) | |
| tree | 80aa3f8cbc000adc228a7a0ca3bbd70225f2f19a /tests | |
| parent | 245724a504528156485bbb32710b5e5444899ce1 (diff) | |
| download | yosys-99706b3bf48de121e58b76d4341d601f0bcc26cd.tar.gz yosys-99706b3bf48de121e58b76d4341d601f0bcc26cd.tar.bz2 yosys-99706b3bf48de121e58b76d4341d601f0bcc26cd.zip | |
Squelch a little more trailing whitespace
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/sva/basic01.sv | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/sva/basic01.sv b/tests/sva/basic01.sv index 74ab93430..d5ad497dd 100644 --- a/tests/sva/basic01.sv +++ b/tests/sva/basic01.sv @@ -6,7 +6,7 @@ module top (input logic clock, ctrl); write <= ctrl; ready <= write; end - + a_rw: assert property ( @(posedge clock) !(read && write) ); `ifdef FAIL a_wr: assert property ( @(posedge clock) write |-> ready ); |