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| author | Miodrag Milanović <mmicko@gmail.com> | 2020-03-14 11:18:27 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-14 11:18:27 +0200 |
| commit | 989e37f4e6f2b46a3e846b4a95b32afdee7fc98f (patch) | |
| tree | 5b7ada9868c5f1a4242a649837d0ceeb94353027 /tests | |
| parent | c0a009139b080078af703bf07f83637ef3c48259 (diff) | |
| parent | 395daf6cedfb62d3a9c6b74b65c80f209d8b6ec5 (diff) | |
| download | yosys-989e37f4e6f2b46a3e846b4a95b32afdee7fc98f.tar.gz yosys-989e37f4e6f2b46a3e846b4a95b32afdee7fc98f.tar.bz2 yosys-989e37f4e6f2b46a3e846b4a95b32afdee7fc98f.zip | |
Merge pull request #1766 from YosysHQ/mmicko/regex_gcc48
Regex support for GCC 4.8
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/logger_error.ys | 6 | ||||
| -rw-r--r-- | tests/various/logger_nowarning.ys | 6 | ||||
| -rw-r--r-- | tests/various/logger_warn.ys | 6 | ||||
| -rw-r--r-- | tests/various/logger_warning.ys | 6 |
4 files changed, 24 insertions, 0 deletions
diff --git a/tests/various/logger_error.ys b/tests/various/logger_error.ys new file mode 100644 index 000000000..46fe7f506 --- /dev/null +++ b/tests/various/logger_error.ys @@ -0,0 +1,6 @@ +logger -werror "is implicitly declared." -expect error "is implicitly declared." 1 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_nowarning.ys b/tests/various/logger_nowarning.ys new file mode 100644 index 000000000..87cbbc644 --- /dev/null +++ b/tests/various/logger_nowarning.ys @@ -0,0 +1,6 @@ +logger -expect-no-warnings -nowarn "is implicitly declared." +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_warn.ys b/tests/various/logger_warn.ys new file mode 100644 index 000000000..2316ae4c6 --- /dev/null +++ b/tests/various/logger_warn.ys @@ -0,0 +1,6 @@ +logger -warn "Successfully finished Verilog frontend." -expect warning "Successfully finished Verilog frontend." 1 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_warning.ys b/tests/various/logger_warning.ys new file mode 100644 index 000000000..642b1b97b --- /dev/null +++ b/tests/various/logger_warning.ys @@ -0,0 +1,6 @@ +logger -expect warning "is implicitly declared." 2 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF |