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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 01:04:29 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-27 01:04:29 -0800 |
| commit | 95053d90109b707103bfbbd2927e6be36d69bca8 (patch) | |
| tree | 74876e66b0eb51d69e97ce6744cad3cdca3781ad /tests | |
| parent | 0466c48533ad2831a95c6b63c3a190adb76499e9 (diff) | |
| parent | 5e67df38edf5207a9b816946b094448cd6a52f88 (diff) | |
| download | yosys-95053d90109b707103bfbbd2927e6be36d69bca8.tar.gz yosys-95053d90109b707103bfbbd2927e6be36d69bca8.tar.bz2 yosys-95053d90109b707103bfbbd2927e6be36d69bca8.zip | |
Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve
write_xaiger improvements
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/simple_abc9/abc9.v | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 64b625efe..4d5879e6f 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -218,12 +218,6 @@ module MUXF8(input I0, I1, S, output O); endmodule // Citation: https://github.com/alexforencich/verilog-ethernet -// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test022" abc9.v -q -// returns before b4321a31 -// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [7] is used but has no -// driver. -// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [3] is used but has no -// driver. module abc9_test022 ( input wire clk, @@ -237,9 +231,6 @@ module abc9_test022 endmodule // Citation: https://github.com/riscv/riscv-bitmanip -// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test023" abc9.v -q -// returns before 14233843 -// Warning: Wire abc9_test023.\dout [1] is used but has no driver. module abc9_test023 #( parameter integer N = 2, parameter integer M = 2 |