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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-19 17:25:39 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-19 17:25:39 +0200 |
| commit | 8395f837c33a1f08ed67995ef8274219b0af27c8 (patch) | |
| tree | e4fa22a4a4598e86f0fa324741fb6062dca851e8 /tests | |
| parent | 5a1f1caa44fb3f4427813acab61aaecc06bae7ba (diff) | |
| parent | ec4565009ae69409eb01f1b595f5f59fcc969ce2 (diff) | |
| download | yosys-8395f837c33a1f08ed67995ef8274219b0af27c8.tar.gz yosys-8395f837c33a1f08ed67995ef8274219b0af27c8.tar.bz2 yosys-8395f837c33a1f08ed67995ef8274219b0af27c8.zip | |
Merge pull request #1109 from YosysHQ/clifford/fix1106
Add "read_verilog -pwires" feature
Diffstat (limited to 'tests')
0 files changed, 0 insertions, 0 deletions