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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-20 13:04:04 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-06-20 13:04:04 +0200 |
| commit | 73bd1d59a7579ea74fb4a201771c983eeaf9a76a (patch) | |
| tree | 831ca8451498c91da804c4e4da33af12728b1589 /tests | |
| parent | 11ec7b2aecddc72747ccdc30d2674583062d58d3 (diff) | |
| parent | 8451cbea896d2b441b5c78eb2813790616d10b84 (diff) | |
| download | yosys-73bd1d59a7579ea74fb4a201771c983eeaf9a76a.tar.gz yosys-73bd1d59a7579ea74fb4a201771c983eeaf9a76a.tar.bz2 yosys-73bd1d59a7579ea74fb4a201771c983eeaf9a76a.zip | |
Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/opt/opt_ff_sat.v | 15 | ||||
| -rw-r--r-- | tests/opt/opt_ff_sat.ys | 4 |
2 files changed, 19 insertions, 0 deletions
diff --git a/tests/opt/opt_ff_sat.v b/tests/opt/opt_ff_sat.v new file mode 100644 index 000000000..fc1e61980 --- /dev/null +++ b/tests/opt/opt_ff_sat.v @@ -0,0 +1,15 @@ +module top( + input clk, + input a, + output b + ); + reg b_reg; + initial begin + b_reg <= 0; + end + + assign b = b_reg; + always @(posedge clk) begin + b_reg <= a && b_reg; + end +endmodule diff --git a/tests/opt/opt_ff_sat.ys b/tests/opt/opt_ff_sat.ys new file mode 100644 index 000000000..13e4ad29b --- /dev/null +++ b/tests/opt/opt_ff_sat.ys @@ -0,0 +1,4 @@ +read_verilog opt_ff_sat.v +prep -flatten +opt_rmdff -sat +synth |