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| author | Sean Cross <sean@xobs.io> | 2019-09-10 08:47:16 +0800 |
|---|---|---|
| committer | Sean Cross <sean@xobs.io> | 2019-09-10 08:47:16 +0800 |
| commit | 702ce405c18c2c28e7f5d354451141d8f16a4085 (patch) | |
| tree | eb7578b82548d602f309354a694cfeba73e0b4fa /tests | |
| parent | 8d128ba6d079fd5f0741c31a9308bf06aaf4673c (diff) | |
| download | yosys-702ce405c18c2c28e7f5d354451141d8f16a4085.tar.gz yosys-702ce405c18c2c28e7f5d354451141d8f16a4085.tar.bz2 yosys-702ce405c18c2c28e7f5d354451141d8f16a4085.zip | |
tests: ice40: fix div_mod SB_LUT4 count
This test is failing due to one of the changes present in this patchset.
Adjust the test to match the newly-observed values.
https://github.com/xobs/yosys/compare/smtbmc-msvc2-build-fixes...YosysHQ:xobs/pr1362
Signed-off-by: Sean Cross <sean@xobs.io>
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/ice40/div_mod.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index 21cac7144..821d6c301 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -4,6 +4,6 @@ flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 62 t:SB_LUT4 +select -assert-count 59 t:SB_LUT4 select -assert-count 41 t:SB_CARRY select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D |