Merge pull request #679 from udif/pr_syntax_error

More meaningful SystemVerilog/Verilog parser error messages

13 files changed, 64 insertions, 0 deletions

diff --git a/tests/errors/syntax_err01.v b/tests/errors/syntax_err01.v
new file mode 100644
index 000000000..68e9b1d50
--- /dev/null
+++ b/tests/errors/syntax_err01.v
@@ -0,0 +1,4 @@
+module a;
+integer [31:0]w;
+endmodule
+
diff --git a/tests/errors/syntax_err02.v b/tests/errors/syntax_err02.v
new file mode 100644
index 000000000..c72e976a8
--- /dev/null
+++ b/tests/errors/syntax_err02.v
@@ -0,0 +1,7 @@
+module a;
+task to (
+  input integer [3:0]x
+);
+endtask
+endmodule
+
diff --git a/tests/errors/syntax_err03.v b/tests/errors/syntax_err03.v
new file mode 100644
index 000000000..6eec44ade
--- /dev/null
+++ b/tests/errors/syntax_err03.v
@@ -0,0 +1,7 @@
+module a;
+task to (
+  input [3]x
+);
+endtask
+endmodule
+
diff --git a/tests/errors/syntax_err04.v b/tests/errors/syntax_err04.v
new file mode 100644
index 000000000..d488e5dbb
--- /dev/null
+++ b/tests/errors/syntax_err04.v
@@ -0,0 +1,4 @@
+module a;
+wire [3]x;
+endmodule
+
diff --git a/tests/errors/syntax_err05.v b/tests/errors/syntax_err05.v
new file mode 100644
index 000000000..8a1f11532
--- /dev/null
+++ b/tests/errors/syntax_err05.v
@@ -0,0 +1,4 @@
+module a;
+input x[2:0];
+endmodule
+
diff --git a/tests/errors/syntax_err06.v b/tests/errors/syntax_err06.v
new file mode 100644
index 000000000..b35a1dea2
--- /dev/null
+++ b/tests/errors/syntax_err06.v
@@ -0,0 +1,6 @@
+module a;
+initial
+begin : label1
+end: label2
+endmodule
+
diff --git a/tests/errors/syntax_err07.v b/tests/errors/syntax_err07.v
new file mode 100644
index 000000000..62bcc6b3e
--- /dev/null
+++ b/tests/errors/syntax_err07.v
@@ -0,0 +1,6 @@
+module a;
+wire [5:0]x;
+wire [3:0]y;
+assign y = (4)55;
+endmodule
+
diff --git a/tests/errors/syntax_err08.v b/tests/errors/syntax_err08.v
new file mode 100644
index 000000000..d41bfd6c9
--- /dev/null
+++ b/tests/errors/syntax_err08.v
@@ -0,0 +1,6 @@
+module a;
+wire [5:0]x;
+wire [3:0]y;
+assign y = x 55;
+endmodule
+
diff --git a/tests/errors/syntax_err09.v b/tests/errors/syntax_err09.v
new file mode 100644
index 000000000..1e472eb94
--- /dev/null
+++ b/tests/errors/syntax_err09.v
@@ -0,0 +1,3 @@
+module a(input wire x = 1'b0);
+endmodule
+
diff --git a/tests/errors/syntax_err10.v b/tests/errors/syntax_err10.v
new file mode 100644
index 000000000..d3280405c
--- /dev/null
+++ b/tests/errors/syntax_err10.v
@@ -0,0 +1,3 @@
+module a;
+parameter integer [2:0]x=0;
+endmodule
diff --git a/tests/errors/syntax_err11.v b/tests/errors/syntax_err11.v
new file mode 100644
index 000000000..f3cde9dfc
--- /dev/null
+++ b/tests/errors/syntax_err11.v
@@ -0,0 +1,3 @@
+module a;
+parameter integer real x=0;
+endmodule
diff --git a/tests/errors/syntax_err12.v b/tests/errors/syntax_err12.v
new file mode 100644
index 000000000..f9b5d5b0b
--- /dev/null
+++ b/tests/errors/syntax_err12.v
@@ -0,0 +1,7 @@
+interface iface;
+endinterface
+
+module a (
+  iface x = 1'b0
+);
+endmodule
diff --git a/tests/errors/syntax_err13.v b/tests/errors/syntax_err13.v
new file mode 100644
index 000000000..b5c942fca
--- /dev/null
+++ b/tests/errors/syntax_err13.v
@@ -0,0 +1,4 @@
+module a #(p = 0)
+();
+endmodule
+