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| author | David Shah <dave@ds0.me> | 2019-09-12 12:26:28 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-12 12:26:28 +0100 |
| commit | 6044fff074f026676312f047cfd5a7c862ff987f (patch) | |
| tree | 67b1bdced6f74eb2551f087df2adb2e17556e974 /tests | |
| parent | f72765090cd001ff4dc54d5a9c01a2d4b3339865 (diff) | |
| parent | c43e52d2d7d16c26b1a4a9c20fad83c9f4577910 (diff) | |
| download | yosys-6044fff074f026676312f047cfd5a7c862ff987f.tar.gz yosys-6044fff074f026676312f047cfd5a7c862ff987f.tar.bz2 yosys-6044fff074f026676312f047cfd5a7c862ff987f.zip | |
Merge pull request #1370 from YosysHQ/dave/equiv_opt_multiclock
Add equiv_opt -multiclock
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/equiv_opt_multiclock.ys | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/various/equiv_opt_multiclock.ys b/tests/various/equiv_opt_multiclock.ys new file mode 100644 index 000000000..81e36d018 --- /dev/null +++ b/tests/various/equiv_opt_multiclock.ys @@ -0,0 +1,12 @@ +read_verilog <<EOT +module top(input clk, pre, d, output reg q); + always @(posedge clk, posedge pre) + if (pre) + q <= 1'b1; + else + q <= d; +endmodule +EOT + +prep +equiv_opt -assert -multiclock -map +/simcells.v synth |