Added defparam support to Verilog/AST frontend

1 files changed, 16 insertions, 0 deletions

diff --git a/tests/simple/paramods.v b/tests/simple/paramods.v
index 94fd2dfc2..8d0134a67 100644
--- a/tests/simple/paramods.v
+++ b/tests/simple/paramods.v
@@ -23,6 +23,22 @@ endmodule
 
 // -----------------------------------
 
+module test3(a, b, x, y);
+
+input [7:0] a, b;
+output [7:0] x, y;
+
+inc inc_a (.in(a), .out(x));
+inc inc_b (b, y);
+
+defparam inc_a.step = 3;
+defparam inc_b.step = 7;
+defparam inc_b.width = 4;
+
+endmodule
+
+// -----------------------------------
+
 module inc(in, out);
 
 parameter width = 8;