sv: allow typenames as function return types

2 files changed, 40 insertions, 0 deletions

diff --git a/tests/verilog/func_typename_ret.sv b/tests/verilog/func_typename_ret.sv
new file mode 100644
index 000000000..423975f97
--- /dev/null
+++ b/tests/verilog/func_typename_ret.sv
@@ -0,0 +1,35 @@
+typedef logic [1:0] T;
+
+package P;
+    typedef logic [3:0] S;
+endpackage
+
+module gate(
+    output wire [31:0] out1, out2
+);
+    function automatic T func1;
+        input reg signed inp;
+        func1 = inp;
+    endfunction
+    assign out1 = func1(1);
+    function automatic P::S func2;
+        input reg signed inp;
+        func2 = inp;
+    endfunction
+    assign out2 = func2(1);
+endmodule
+
+module gold(
+    output wire [31:0] out1, out2
+);
+    function automatic [1:0] func1;
+        input reg signed inp;
+        func1 = inp;
+    endfunction
+    assign out1 = func1(1);
+    function automatic [3:0] func2;
+        input reg signed inp;
+        func2 = inp;
+    endfunction
+    assign out2 = func2(1);
+endmodule
diff --git a/tests/verilog/func_typename_ret.ys b/tests/verilog/func_typename_ret.ys
new file mode 100644
index 000000000..7f6049961
--- /dev/null
+++ b/tests/verilog/func_typename_ret.ys
@@ -0,0 +1,5 @@
+read_verilog -sv func_typename_ret.sv
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert