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author | Clifford Wolf <clifford@clifford.at> | 2018-02-28 15:32:53 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2018-02-28 15:32:53 +0100 |
commit | 3df0d04a7b7ac01e94d3e2fcf376b8ab4f7de90e (patch) | |
tree | b745bb0a4129a512fc8dc1460bf79c8674a88482 /tests | |
parent | 6f26695d9b596fe3b221334a93c5d94678582aea (diff) | |
parent | 5ac3ee858a35bf4dd20c02a3cfcd9c0e23db9ecc (diff) | |
download | yosys-3df0d04a7b7ac01e94d3e2fcf376b8ab4f7de90e.tar.gz yosys-3df0d04a7b7ac01e94d3e2fcf376b8ab4f7de90e.tar.bz2 yosys-3df0d04a7b7ac01e94d3e2fcf376b8ab4f7de90e.zip |
Merge branch 'verificsva-ng'
Diffstat (limited to 'tests')
-rw-r--r-- | tests/sva/sva_range.sv | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/sva/sva_range.sv b/tests/sva/sva_range.sv index 38199bff1..d1569fc83 100644 --- a/tests/sva/sva_range.sv +++ b/tests/sva/sva_range.sv @@ -5,7 +5,7 @@ module top ( default clocking @(posedge clk); endclocking assert property ( - a ##[*] b |=> c until ##[*] d + a ##[*] b |=> c until d ); `ifndef FAIL |