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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-20 15:42:29 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-20 15:42:29 -0700 |
| commit | 38ee59184ca50b37b4adacb957f553391b7769d4 (patch) | |
| tree | ef52338f998c063b3489b7963637459bb428dfef /tests | |
| parent | c506da3819613fcfa5c0cfe73865ca0bacadb52c (diff) | |
| download | yosys-38ee59184ca50b37b4adacb957f553391b7769d4.tar.gz yosys-38ee59184ca50b37b4adacb957f553391b7769d4.tar.bz2 yosys-38ee59184ca50b37b4adacb957f553391b7769d4.zip | |
tests: remove write_ilang
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/ecp5/memories.ys | 2 | ||||
| -rw-r--r-- | tests/arch/ice40/memories.ys | 1 |
2 files changed, 0 insertions, 3 deletions
diff --git a/tests/arch/ecp5/memories.ys b/tests/arch/ecp5/memories.ys index e1f748e26..f55bf01d2 100644 --- a/tests/arch/ecp5/memories.ys +++ b/tests/arch/ecp5/memories.ys @@ -208,7 +208,6 @@ select -assert-count 1 t:PDPW16KD design -reset; read_verilog ../common/blockrom.v chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom -write_ilang synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 0 t:PDPW16KD # too inefficient select -assert-min 18 t:LUT4 @@ -274,7 +273,6 @@ select -assert-count 1 t:DP16KD design -reset; read_verilog ../common/blockrom.v chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom -write_ilang synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 0 t:DP16KD # too inefficient select -assert-min 9 t:LUT4 diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys index 571edec1d..c32f12315 100644 --- a/tests/arch/ice40/memories.ys +++ b/tests/arch/ice40/memories.ys @@ -112,7 +112,6 @@ select -assert-count 1 t:SB_RAM40_4K design -reset; read_verilog ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom -write_ilang synth_ice40 -top sync_rom; cd sync_rom select -assert-count 0 t:SB_RAM40_4K # too inefficient select -assert-min 1 t:SB_LUT4 |