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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-22 10:24:42 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-22 10:24:42 +0200 |
| commit | 34a7c0209d23e8905009c4c122f850be6dd3ac05 (patch) | |
| tree | e31e510677449df802edce200ccb85bae5060ad0 /tests | |
| parent | 841903582f5f063fa1f8de7fbfaed7ac7eca373a (diff) | |
| parent | a6776ee35ee5404ca7d5b63fd2daccc46354112c (diff) | |
| download | yosys-34a7c0209d23e8905009c4c122f850be6dd3ac05.tar.gz yosys-34a7c0209d23e8905009c4c122f850be6dd3ac05.tar.bz2 yosys-34a7c0209d23e8905009c4c122f850be6dd3ac05.zip | |
Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg
mem2reg to preserve user attributes and src
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/mem2reg.ys | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/various/mem2reg.ys b/tests/various/mem2reg.ys new file mode 100644 index 000000000..00389c700 --- /dev/null +++ b/tests/various/mem2reg.ys @@ -0,0 +1,13 @@ +read_verilog <<EOT +module top; +parameter DATADEPTH=2; +parameter DATAWIDTH=1; +(* keep, nomem2reg *) reg [DATAWIDTH-1:0] data1 [DATADEPTH-1:0]; +(* keep, mem2reg *) reg [DATAWIDTH-1:0] data2 [DATADEPTH-1:0]; +endmodule +EOT + +proc +cd top +select -assert-count 1 m:data1 a:src=<<EOT:4 %i +select -assert-count 2 w:data2[*] a:src=<<EOT:5 %i |