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author | Clifford Wolf <clifford@clifford.at> | 2016-04-21 12:06:07 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-04-21 14:22:58 +0200 |
commit | 1761d08dd239bcf1765ebf807fc22514edac387f (patch) | |
tree | ae85382cf669082b7d8427d59ceb32e77b9e3c13 /tests | |
parent | bf64974d43600b2e8ad63a1762489a152c002a41 (diff) | |
download | yosys-1761d08dd239bcf1765ebf807fc22514edac387f.tar.gz yosys-1761d08dd239bcf1765ebf807fc22514edac387f.tar.bz2 yosys-1761d08dd239bcf1765ebf807fc22514edac387f.zip |
Bugfix and improvements in memory_share
Diffstat (limited to 'tests')
-rw-r--r-- | tests/simple/memory.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/simple/memory.v b/tests/simple/memory.v index d58ed9d1a..9fddce26c 100644 --- a/tests/simple/memory.v +++ b/tests/simple/memory.v @@ -243,3 +243,24 @@ module memtest10(input clk, input [5:0] din, output [5:0] dout); assign dout = queue[3]; endmodule + +// ---------------------------------------------------------- + +module memtest11(clk, wen, waddr, raddr, wdata, rdata); + input clk, wen; + input [1:0] waddr, raddr; + input [7:0] wdata; + output [7:0] rdata; + + reg [7:0] mem [3:0]; + + assign rdata = mem[raddr]; + + always @(posedge clk) begin + if (wen) + mem[waddr] <= wdata; + else + mem[waddr] <= mem[waddr]; + end +endmodule + |