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authorEddie Hung <eddie@fpgeh.com>2019-09-11 09:09:08 -0700
committerEddie Hung <eddie@fpgeh.com>2019-09-11 09:09:08 -0700
commit36d6db7f8aac6568acc2fb2d4ea5a5427d00d667 (patch)
tree3b2dfabe6f5677b9042b22d8c55a013c04862d56 /tests/xilinx/macc.v
parentded805ae5d9d9884be319a710f159007e73c9636 (diff)
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Extend test for RSTP and RSTM
Diffstat (limited to 'tests/xilinx/macc.v')
-rw-r--r--tests/xilinx/macc.v36
1 files changed, 34 insertions, 2 deletions
diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v
index 0bb673316..c6ad2a578 100644
--- a/tests/xilinx/macc.v
+++ b/tests/xilinx/macc.v
@@ -35,7 +35,39 @@ always @(posedge clk)
adder_out <= old_result + mult_reg;
end
- // Output accumulation result
- assign accum_out = adder_out;
+// Output accumulation result
+assign accum_out = adder_out;
+
+endmodule
+
+// Adapted variant of above
+module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) (
+ input clk, ce, rst,
+ input signed [SIZEIN-1:0] a, b,
+ output signed [SIZEOUT-1:0] accum_out
+);
+// Declare registers for intermediate values
+reg signed [SIZEIN-1:0] a_reg, b_reg;
+reg rst_reg;
+reg signed [2*SIZEIN-1:0] mult_reg;
+reg signed [SIZEOUT-1:0] adder_out, old_result;
+always @(posedge clk) begin
+ if (ce)
+ begin
+ a_reg <= a;
+ b_reg <= b;
+ mult_reg <= a_reg * b_reg;
+ rst_reg <= rst;
+ // Store accumulation result into a register
+ adder_out <= adder_out + mult_reg;
+ end
+ if (rst) begin
+ mult_reg <= 0;
+ adder_out <= 0;
+ end
+end
+
+// Output accumulation result
+assign accum_out = adder_out;
endmodule