diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-27 12:50:20 -0700 |
|---|---|---|
| committer | Marcin Kościelnicki <koriakin@0x04.net> | 2019-09-30 12:52:43 +0200 |
| commit | 6216e45edae11fa3cc6e45a65762e5c215af0904 (patch) | |
| tree | efaa84b394220244d219a85b9cea35e7920bfa24 /tests/xilinx/latches.ys | |
| parent | 5b5756b91ee6b514021afbe857135801f3cdcc33 (diff) | |
| download | yosys-6216e45edae11fa3cc6e45a65762e5c215af0904.tar.gz yosys-6216e45edae11fa3cc6e45a65762e5c215af0904.tar.bz2 yosys-6216e45edae11fa3cc6e45a65762e5c215af0904.zip | |
Add latch test modified from #1363
Diffstat (limited to 'tests/xilinx/latches.ys')
| -rw-r--r-- | tests/xilinx/latches.ys | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys new file mode 100644 index 000000000..ac1102896 --- /dev/null +++ b/tests/xilinx/latches.ys @@ -0,0 +1,15 @@ +read_verilog latches.v + +proc +flatten +equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +async2sync +equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check + +design -load preopt +synth_xilinx +cd top +select -assert-count 1 t:LUT1 +select -assert-count 2 t:LUT3 +select -assert-count 3 t:LDCE +select -assert-none t:LUT1 t:LUT3 t:LDCE %% t:* %D |