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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:24:53 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:24:53 +0200 |
| commit | 980df499abb63e5dfadc29b3326032b55b6dbf18 (patch) | |
| tree | d4266e4c30eb1ad9fdd91ab871609b28ba3c1865 /tests/xilinx/counter.ys | |
| parent | b2f0d75807c99c74f9860098b74e8300514ba9e5 (diff) | |
| download | yosys-980df499abb63e5dfadc29b3326032b55b6dbf18.tar.gz yosys-980df499abb63e5dfadc29b3326032b55b6dbf18.tar.bz2 yosys-980df499abb63e5dfadc29b3326032b55b6dbf18.zip | |
Make equivalence work with latest master
Diffstat (limited to 'tests/xilinx/counter.ys')
| -rw-r--r-- | tests/xilinx/counter.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys index 3bb3a8eb0..459541656 100644 --- a/tests/xilinx/counter.ys +++ b/tests/xilinx/counter.ys @@ -2,7 +2,7 @@ read_verilog counter.v hierarchy -top top proc flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module |