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authorZachary Snow <zach@zachjs.com>2021-03-16 11:06:40 -0400
committerZachary Snow <zachary.j.snow@gmail.com>2021-03-17 15:53:52 -0400
commitf71c2dcca6b63ad3cbd3d5b6f51f67f9cd85f03e (patch)
tree4edd598b167d6422f64743b30587ead247346e46 /tests/verilog
parent092e923330ce23adffa7843a27bdba8a0b139e58 (diff)
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sv: carry over global typedefs from previous files
This breaks the ability to use a global typename as a standard identifier in a subsequent input file. This is otherwise backwards compatible, including for sources which previously included conflicting typedefs in each input file.
Diffstat (limited to 'tests/verilog')
-rw-r--r--tests/verilog/typedef_across_files.ys23
-rw-r--r--tests/verilog/typedef_legacy_conflict.ys37
2 files changed, 60 insertions, 0 deletions
diff --git a/tests/verilog/typedef_across_files.ys b/tests/verilog/typedef_across_files.ys
new file mode 100644
index 000000000..ca9bba736
--- /dev/null
+++ b/tests/verilog/typedef_across_files.ys
@@ -0,0 +1,23 @@
+read_verilog -sv <<EOF
+typedef logic T;
+EOF
+
+read_verilog -sv <<EOF
+typedef T [3:0] S;
+EOF
+
+read_verilog -sv <<EOF
+module top;
+ T t;
+ S s;
+ always @* begin
+ assert ($bits(t) == 1);
+ assert ($bits(s) == 4);
+ end
+endmodule
+EOF
+
+proc
+opt -full
+select -module top
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/tests/verilog/typedef_legacy_conflict.ys b/tests/verilog/typedef_legacy_conflict.ys
new file mode 100644
index 000000000..8dff4ec5f
--- /dev/null
+++ b/tests/verilog/typedef_legacy_conflict.ys
@@ -0,0 +1,37 @@
+read_verilog -sv <<EOF
+typedef logic T;
+typedef T [3:0] S;
+EOF
+
+read_verilog -sv <<EOF
+module example;
+ // S and T refer to the definitions from the first file
+ T t;
+ S s;
+ always @* begin
+ assert ($bits(t) == 1);
+ assert ($bits(s) == 4);
+ end
+endmodule
+
+typedef byte T;
+typedef T S;
+
+module top;
+ // S and T refer to the most recent overrides
+ T t;
+ S s;
+ always @* begin
+ assert ($bits(t) == 8);
+ assert ($bits(s) == 8);
+ end
+ example e();
+endmodule
+EOF
+
+hierarchy
+proc
+flatten
+opt -full
+select -module top
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all