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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 13:22:41 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 13:22:41 -0700 |
| commit | f46ef47893b4d2cb01fc5914fe0ee89d206f686f (patch) | |
| tree | b9be5ae6affadc6cca1d36f3cb3a5c84474de244 /tests/various | |
| parent | bbef0d2ac8a84299109d9bd93b5eb69a5500d594 (diff) | |
| download | yosys-f46ef47893b4d2cb01fc5914fe0ee89d206f686f.tar.gz yosys-f46ef47893b4d2cb01fc5914fe0ee89d206f686f.tar.bz2 yosys-f46ef47893b4d2cb01fc5914fe0ee89d206f686f.zip | |
Add more tests
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/peepopt.ys | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 2a660d5c9..8dce679ff 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -78,3 +78,35 @@ clean select -assert-count 1 t:$dff r:WIDTH=2 %i select -assert-count 1 t:$mux r:WIDTH=2 %i select -assert-count 0 t:$dff t:$mux %% t:* %D + +################### + +design -reset +read_verilog <<EOT +module peepopt_dffmuxext_const(input clk, ce, input [1:0] i, output reg [5:0] o); + always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz}; +endmodule +EOT + +proc +equiv_opt -assert peepopt +design -load postopt +select -assert-count 1 t:$dff r:WIDTH=2 %i +select -assert-count 1 t:$mux r:WIDTH=2 %i +select -assert-count 0 t:$dff t:$mux %% t:* %D + +################### + +design -reset +read_verilog <<EOT +module peepopt_dffmuxext_const_init(input clk, ce, input [1:0] i, (* init=6'b0x00x1 *) output reg [5:0] o); + always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz}; +endmodule +EOT + +proc +equiv_opt -assert peepopt +design -load postopt +select -assert-count 1 t:$dff r:WIDTH=5 %i +select -assert-count 1 t:$mux r:WIDTH=5 %i +select -assert-count 0 t:$dff t:$mux %% t:* %D |