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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 10:12:48 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 10:12:48 -0700 |
| commit | dc677c791de438a493ad5e0101987da29c6a6d0f (patch) | |
| tree | cc066adc0cefdd7cb187680e4ca81b790535fd81 /tests/various | |
| parent | af744097496702926f4fbff5d6eb889ad82fa6cf (diff) | |
| download | yosys-dc677c791de438a493ad5e0101987da29c6a6d0f.tar.gz yosys-dc677c791de438a493ad5e0101987da29c6a6d0f.tar.bz2 yosys-dc677c791de438a493ad5e0101987da29c6a6d0f.zip | |
Add test from #1144, and try reading without '-specify' flag
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/specify.v | 14 | ||||
| -rw-r--r-- | tests/various/specify.ys | 2 |
2 files changed, 16 insertions, 0 deletions
diff --git a/tests/various/specify.v b/tests/various/specify.v index afc421da8..b1f399267 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -28,3 +28,17 @@ module test2 ( (B => Q) = 1.5; endspecify endmodule + +module issue01144(input clk, d, output q); +specify + // Fails: + (posedge clk => (q +: d)) = (3,1); + (/*posedge*/ clk => (q +: d)) = (3,1); + (posedge clk *> (q +: d)) = (3,1); + (/*posedge*/ clk *> (q +: d)) = (3,1); + + // Works: + (/*posedge*/ clk => q) = (3,1); + (/*posedge*/ clk *> q) = (3,1); +endspecify +endmodule diff --git a/tests/various/specify.ys b/tests/various/specify.ys index a5ca07219..a2b6038e4 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -54,3 +54,5 @@ equiv_struct equiv_induct -seq 5 equiv_status -assert design -reset + +read_verilog specify.v |