Merge branch 'master' into clk2ff-better-names

8 files changed, 252 insertions, 9 deletions

diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index a9880c722..e0add714b 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -90,7 +90,7 @@ $_DFF_N_ ff4(.C(clk), .D(1'b1), .Q(z));
 endmodule
 EOT
 simplemap
-equiv_opt abc9 -lut 4 -dff
+equiv_opt -assert abc9 -lut 4 -dff
 design -load postopt
 cd abc9_test038
 select -assert-count 3 t:$_DFF_N_
@@ -99,3 +99,58 @@ clean
 select -assert-count 2 a:init
 select -assert-count 1 w:w a:init %i
 select -assert-count 1 c:ff4 %co c:ff4 %d %a a:init %i
+
+
+# Check that non-dangling ABC9 black-boxes are preserved
+design -reset
+read_verilog -specify <<EOT
+(* abc9_box, blackbox *)
+module mux_with_param(input I0, I1, S, output O);
+parameter P = 0;
+specify
+    (I0 => O) = P;
+    (I1 => O) = P;
+    (S => O) = P;
+endspecify
+endmodule
+
+module abc9_test039(output O);
+  mux_with_param #(.P(1)) m (
+    .I0(1'b1),
+    .I1(1'b1),
+    .O(O),
+    .S(1'b0)
+  );
+endmodule
+EOT
+abc9 -lut 4
+cd abc9_test039
+select -assert-count 1 t:mux_with_param
+
+
+# Check that dangling ABC9 black-boxes are swept away
+design -reset
+read_verilog -specify <<EOT
+(* abc9_box, blackbox *)
+module mux_with_param(input I0, I1, S, output O);
+parameter P = 0;
+specify
+    (I0 => O) = P;
+    (I1 => O) = P;
+    (S => O) = P;
+endspecify
+endmodule
+
+module abc9_test040(output O);
+  wire w;
+  mux_with_param #(.P(1)) m (
+    .I0(1'b1),
+    .I1(1'b1),
+    .O(w),
+    .S(1'b0)
+  );
+endmodule
+EOT
+abc9 -lut 4
+cd abc9_test040
+select -assert-count 0 t:mux_with_param
diff --git a/tests/various/async.sh b/tests/various/async.sh
index 7c41d6d94..e83935d02 100644
--- a/tests/various/async.sh
+++ b/tests/various/async.sh
@@ -1,9 +1,9 @@
 #!/bin/bash
 set -ex
-../../yosys -q -o async_syn.v -p 'synth; rename uut syn' async.v
-../../yosys -q -o async_prp.v -p 'prep; rename uut prp' async.v
-../../yosys -q -o async_a2s.v -p 'prep; async2sync; rename uut a2s' async.v
-../../yosys -q -o async_ffl.v -p 'prep; clk2fflogic; rename uut ffl' async.v
+../../yosys -q -o async_syn.v -r uut -p 'synth; rename uut syn' async.v
+../../yosys -q -o async_prp.v -r uut -p 'prep; rename uut prp' async.v
+../../yosys -q -o async_a2s.v -r uut -p 'prep; async2sync; rename uut a2s' async.v
+../../yosys -q -o async_ffl.v -r uut -p 'prep; clk2fflogic; rename uut ffl' async.v
 iverilog -o async_sim -DTESTBENCH async.v async_???.v
 vvp -N async_sim > async.out
 tail async.out
diff --git a/tests/various/blackbox_wb.ys b/tests/various/blackbox_wb.ys
new file mode 100644
index 000000000..f9c9bec06
--- /dev/null
+++ b/tests/various/blackbox_wb.ys
@@ -0,0 +1,14 @@
+read_verilog <<EOT
+(* whitebox *)
+module box(input a, output q);
+assign q = ~a;
+endmodule
+
+module top(input a, output q);
+box box_i(.a(a), .q(q));
+endmodule
+EOT
+select -assert-count 1 =box/t:$not
+blackbox =box
+select -assert-count 0 =A:whitebox
+select -assert-count 0 =box/t:$not
diff --git a/tests/various/logger_fail.sh b/tests/various/logger_fail.sh
new file mode 100755
index 000000000..19b650007
--- /dev/null
+++ b/tests/various/logger_fail.sh
@@ -0,0 +1,42 @@
+#!/bin/bash
+
+fail() {
+	echo "$1" >&2
+	exit 1
+}
+
+runTest() {
+	desc="$1"
+	want="$2"
+	shift 2
+	echo "running '$desc' with args $@"
+	output=`../../yosys -q "$@" 2>&1`
+	if [ $? -ne 1 ]; then
+		fail "exit code for '$desc' was not 1"
+	fi
+	if [ "$output" != "$want" ]; then
+		fail "output for '$desc' did not match"
+	fi
+}
+
+unmet() {
+	kind=$1
+	runTest "unmet $kind" \
+		"ERROR: Expected $kind pattern 'foobar' not found !" \
+		-p "logger -expect $kind \"foobar\" 1"
+}
+
+unmet log
+unmet warning
+unmet error
+
+runTest "too many logs" \
+	"ERROR: Expected log pattern 'statistics' found 2 time(s), instead of 1 time(s) !" \
+	-p "logger -expect log \"statistics\" 1" -p stat -p stat
+
+runTest "too many warnings" \
+	"Warning: Found log message matching -W regex:
+Printing statistics.
+ERROR: Expected warning pattern 'statistics' found 2 time(s), instead of 1 time(s) !" \
+	-p "logger -warn \"Printing statistics\"" \
+	-p "logger -expect warning \"statistics\" 1" -p stat -p stat
diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 33ece1f16..752f9ba48 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -154,7 +154,7 @@ always @*
      o <= i[4*W+:W];
 endmodule
 
-module cliffordwolf_nonexclusive_select (
+module clairexen_nonexclusive_select (
         input wire x, y, z,
         input wire a, b, c, d,
         output reg o
@@ -167,7 +167,7 @@ module cliffordwolf_nonexclusive_select (
         end
 endmodule
 
-module cliffordwolf_freduce (
+module clairexen_freduce (
         input wire [1:0] s,
         input wire a, b, c, d,
         output reg [3:0] o
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 3e90419af..d73fc44b4 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -167,7 +167,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
 design -load read
-hierarchy -top cliffordwolf_nonexclusive_select
+hierarchy -top clairexen_nonexclusive_select
 prep
 design -save gold
 muxpack
@@ -182,7 +182,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
 #design -load read
-#hierarchy -top cliffordwolf_freduce
+#hierarchy -top clairexen_freduce
 #prep
 #design -save gold
 #proc; opt; freduce; opt
diff --git a/tests/various/param_struct.ys b/tests/various/param_struct.ys
new file mode 100644
index 000000000..6d7a7c6ad
--- /dev/null
+++ b/tests/various/param_struct.ys
@@ -0,0 +1,51 @@
+read_verilog -sv << EOF
+package p;
+typedef struct packed {
+  logic a;
+  logic b;
+} struct_t;
+
+typedef struct packed {
+  struct_t g;
+  logic [2:0] h;
+} nested_struct_t;
+
+typedef union packed {
+  logic [4:0] x;
+} nested_union_t;
+
+parameter struct_t c = {1'b1, 1'b0};
+parameter nested_struct_t x = {{1'b1, 1'b0}, 1'b1, 1'b1, 1'b1};
+endpackage
+
+module dut ();
+parameter p::struct_t d = p::c;
+parameter p::nested_struct_t i = p::x;
+
+parameter p::nested_union_t u = {5'b11001};
+
+localparam e = d.a;
+localparam f = d.b;
+
+localparam j = i.g.a;
+localparam k = i.g.b;
+localparam l = i.h;
+localparam m = i.g;
+
+localparam o = u.x;
+
+always_comb begin
+  assert(d == 2'b10);
+  assert(e == 1'b1);
+  assert(f == 1'b0);
+  assert(j == 1'b1);
+  assert(k == 1'b0);
+  assert(l == 3'b111);
+// TODO: support access to whole sub-structs and unions
+//  assert(m == 2'b10);
+  assert(u == 5'b11001);
+end
+endmodule
+EOF
+hierarchy; proc; opt
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/tests/various/sta.ys b/tests/various/sta.ys
new file mode 100644
index 000000000..156c31c47
--- /dev/null
+++ b/tests/various/sta.ys
@@ -0,0 +1,81 @@
+read_verilog -specify <<EOT
+module buffer(input i, output o);
+specify
+(i => o) = 10;
+endspecify
+endmodule
+
+module top(input i);
+wire w;
+buffer b(.i(i), .o(w));
+endmodule
+EOT
+
+logger -expect warning "Critical-path does not terminate in a recognised endpoint\." 1
+sta
+
+
+design -reset
+read_verilog -specify <<EOT
+module top(input i, output o, p);
+assign o = i;
+endmodule
+EOT
+
+logger -expect log "No timing paths found\." 1
+sta
+
+
+design -reset
+read_verilog -specify <<EOT
+module buffer(input i, output o);
+specify
+(i => o) = 10;
+endspecify
+endmodule
+
+module top(input i, output o, p);
+buffer b(.i(i), .o(o));
+endmodule
+EOT
+
+sta
+
+
+design -reset
+read_verilog -specify <<EOT
+module buffer(input i, output o);
+specify
+(i => o) = 10;
+endspecify
+endmodule
+
+module top(input i, output o, p);
+buffer b(.i(i), .o(o));
+const0 c(.o(p));
+endmodule
+EOT
+
+logger -expect warning "Cell type 'const0' not recognised! Ignoring\." 1
+sta
+
+
+design -reset
+read_verilog -specify <<EOT
+module buffer(input i, output o);
+specify
+(i => o) = 10;
+endspecify
+endmodule
+module const0(output o);
+endmodule
+
+module top(input i, output o, p);
+buffer b(.i(i), .o(o));
+const0 c(.o(p));
+endmodule
+EOT
+
+sta
+
+logger -expect-no-warnings