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author | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 13:01:34 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 13:01:34 -0700 |
commit | 38e73a3788a4e53b81f4c4882eeea23a8f6d0f7e (patch) | |
tree | 721c125712cf68d86716ea331c8214b9931b577c /tests/various | |
parent | e742478e1d4ffc93efd8dfe6f6d7fb53eef0305e (diff) | |
parent | ef0681ea4ca0b34689cbf14d5a4478e2785600d9 (diff) | |
download | yosys-38e73a3788a4e53b81f4c4882eeea23a8f6d0f7e.tar.gz yosys-38e73a3788a4e53b81f4c4882eeea23a8f6d0f7e.tar.bz2 yosys-38e73a3788a4e53b81f4c4882eeea23a8f6d0f7e.zip |
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
Diffstat (limited to 'tests/various')
-rw-r--r-- | tests/various/peepopt.ys | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys new file mode 100644 index 000000000..91db22423 --- /dev/null +++ b/tests/various/peepopt.ys @@ -0,0 +1,63 @@ +read_verilog <<EOT +module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o); +assign o = i[s*W+:W]; +endmodule +EOT + +prep -nokeepdc +equiv_opt peepopt +design -load postopt +clean +select -assert-count 1 t:$shiftx +select -assert-count 0 t:$shiftx t:* %D + +#################### + +design -reset +read_verilog <<EOT +module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w); +assign y = 1'b1 >> (w * (3'b110)); +endmodule +EOT + +prep -nokeepdc +equiv_opt peepopt +design -load postopt +clean +select -assert-count 1 t:$shr +select -assert-count 1 t:$mul +select -assert-count 0 t:$shr t:$mul %% t:* %D + +#################### + +design -reset +read_verilog <<EOT +module peepopt_muldiv_0(input [1:0] i, output [1:0] o); +wire [3:0] t; +assign t = i * 3; +assign o = t / 3; +endmodule +EOT + +prep -nokeepdc +equiv_opt peepopt +design -load postopt +clean +select -assert-count 0 t:* + +#################### + +design -reset +read_verilog <<EOT +module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o); + always @(posedge clk) if (ce) o <= i; +endmodule +EOT + +prep -nokeepdc +equiv_opt peepopt +design -load postopt +clean +select -assert-count 1 t:$dff r:WIDTH=2 %i +select -assert-count 1 t:$mux r:WIDTH=2 %i +select -assert-count 0 t:$dff t:$mux %% t:* %D |