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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 00:29:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:57 -0700 |
| commit | 13f9d65b6fc09af76330c02ab420324b50db61da (patch) | |
| tree | c2e403d93adf7e029feb4c489ac45cb6ac89d634 /tests/various | |
| parent | fa31e84112c004348fae30e64ca224367b71d187 (diff) | |
| download | yosys-13f9d65b6fc09af76330c02ab420324b50db61da.tar.gz yosys-13f9d65b6fc09af76330c02ab420324b50db61da.tar.bz2 yosys-13f9d65b6fc09af76330c02ab420324b50db61da.zip | |
abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/abc9.ys | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 9586091c4..ac714665f 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -78,18 +78,23 @@ abc9 design -reset read_verilog -icells <<EOT -module abc9_test038(input clk, output w, x, y); +module abc9_test038(input clk, output w, x, y, z); (* init=1'b1 *) wire w; $_DFF_N_ ff1(.C(clk), .D(1'b1), .Q(w)); (* init=1'bx *) wire x; $_DFF_N_ ff2(.C(clk), .D(1'b0), .Q(x)); (* init=1'b0 *) wire y; $_DFF_N_ ff3(.C(clk), .D(1'b0), .Q(y)); +(* init=1'b0 *) wire z; +$_DFF_N_ ff4(.C(clk), .D(1'b1), .Q(z)); endmodule EOT simplemap equiv_opt abc9 -lut 4 -dff design -load postopt cd abc9_test038 -select -assert-count 2 t:$_DFF_N_ -select -assert-none c:ff1 c:ff2 %% c:* %D +select -assert-count 3 t:$_DFF_N_ +select -assert-none c:ff1 c:ff2 c:ff4 %% c:* %D +clean +select -assert-count 2 a:init +select -assert-none w:w w:z %% a:init %D |