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| author | clairexen <claire@symbioticeda.com> | 2020-07-15 11:49:09 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-15 11:49:09 +0200 |
| commit | 021ce8e59646ed9a6dff4447e11cceae9d3e615c (patch) | |
| tree | 175394ccfbc749c48f3ac0e057db630c7e78d566 /tests/various | |
| parent | 61a7ec4768a3d0d0c8875bb4d9b6160f8697c0d6 (diff) | |
| parent | 02c071888b4b2a26db5653609bb60e6c3f5c366f (diff) | |
| download | yosys-021ce8e59646ed9a6dff4447e11cceae9d3e615c.tar.gz yosys-021ce8e59646ed9a6dff4447e11cceae9d3e615c.tar.bz2 yosys-021ce8e59646ed9a6dff4447e11cceae9d3e615c.zip | |
Merge pull request #2257 from antmicro/fix-conflicts
Restore #2203 and #2244 and fix parser conflicts
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/integer_range_bad_syntax.ys | 6 | ||||
| -rw-r--r-- | tests/various/integer_real_bad_syntax.ys | 6 | ||||
| -rw-r--r-- | tests/various/logic_param_simple.ys | 9 | ||||
| -rw-r--r-- | tests/various/signed.ys | 28 |
4 files changed, 49 insertions, 0 deletions
diff --git a/tests/various/integer_range_bad_syntax.ys b/tests/various/integer_range_bad_syntax.ys new file mode 100644 index 000000000..4f427211f --- /dev/null +++ b/tests/various/integer_range_bad_syntax.ys @@ -0,0 +1,6 @@ +logger -expect error "syntax error, unexpected" 1 +read_verilog -sv <<EOT +module test_integer_range(); +parameter integer [31:0] a = 0; +endmodule +EOT diff --git a/tests/various/integer_real_bad_syntax.ys b/tests/various/integer_real_bad_syntax.ys new file mode 100644 index 000000000..942d8de77 --- /dev/null +++ b/tests/various/integer_real_bad_syntax.ys @@ -0,0 +1,6 @@ +logger -expect error "syntax error, unexpected TOK_REAL" 1 +read_verilog -sv <<EOT +module test_integer_real(); +parameter integer real a = 0; +endmodule +EOT diff --git a/tests/various/logic_param_simple.ys b/tests/various/logic_param_simple.ys new file mode 100644 index 000000000..968564080 --- /dev/null +++ b/tests/various/logic_param_simple.ys @@ -0,0 +1,9 @@ +read_verilog -sv <<EOT +module test_logic_param(); +parameter logic a = 0; +parameter logic [31:0] e = 0; +parameter logic signed b = 0; +parameter logic unsigned c = 0; +parameter logic unsigned [31:0] d = 0; +endmodule +EOT diff --git a/tests/various/signed.ys b/tests/various/signed.ys new file mode 100644 index 000000000..2319a5da1 --- /dev/null +++ b/tests/various/signed.ys @@ -0,0 +1,28 @@ +# SV LRM A2.2.1 + +read_verilog -sv <<EOT +module test_signed(); +parameter integer signed a = 0; +parameter integer unsigned b = 0; + +endmodule +EOT + +design -reset +read_verilog -sv <<EOT +module test_signed(); +parameter logic signed [7:0] a = 0; +parameter logic unsigned [7:0] b = 0; + +endmodule +EOT + +design -reset +logger -expect error "syntax error, unexpected TOK_INTEGER" 1 +read_verilog -sv <<EOT +module test_signed(); +parameter signed integer a = 0; +parameter unsigned integer b = 0; + +endmodule +EOT |