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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-12 12:06:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-12 12:06:45 -0700 |
| commit | 12c692f6eda7367527fde2a8aad49447a73aa643 (patch) | |
| tree | 8680eefff6897b2f4b33d12b5d96a6ea8c549b5b /tests/various/wreduce.ys | |
| parent | 78b30bbb1102047585d1a2eac89b1c7f5ca7344e (diff) | |
| download | yosys-12c692f6eda7367527fde2a8aad49447a73aa643.tar.gz yosys-12c692f6eda7367527fde2a8aad49447a73aa643.tar.bz2 yosys-12c692f6eda7367527fde2a8aad49447a73aa643.zip | |
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing
changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
Diffstat (limited to 'tests/various/wreduce.ys')
| -rw-r--r-- | tests/various/wreduce.ys | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys index 4257292f5..2e0812c48 100644 --- a/tests/various/wreduce.ys +++ b/tests/various/wreduce.ys @@ -36,7 +36,6 @@ design -save gold opt_expr wreduce -dump select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i design -stash gate @@ -46,3 +45,35 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +########## + +# Testcase from: https://github.com/YosysHQ/yosys/commit/25680f6a078bb32f157bd580705656496717bafb +design -reset +read_verilog <<EOT +module top( + input clk, + input rst, + input [2:0] a, + output [1:0] b +); + reg [2:0] b_reg; + initial begin + b_reg <= 3'b0; + end + + assign b = b_reg[1:0]; + always @(posedge clk or posedge rst) begin + if(rst) begin + b_reg <= 3'b0; + end else begin + b_reg <= a; + end + end +endmodule +EOT + +proc +wreduce + +select -assert-count 1 t:$adff r:ARST_VALUE=2'b00 %i |