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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 17:22:18 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 17:22:18 +0200 |
| commit | b21ebe1859df2f9bd1791de34633a85918651c13 (patch) | |
| tree | d7275964e645dcda208951b1969243dbd96b011e /tests/various/submod_extract.ys | |
| parent | 267c61564047f8768c29040f898633d9444a5404 (diff) | |
| download | yosys-b21ebe1859df2f9bd1791de34633a85918651c13.tar.gz yosys-b21ebe1859df2f9bd1791de34633a85918651c13.tar.bz2 yosys-b21ebe1859df2f9bd1791de34633a85918651c13.zip | |
Added tests/various/submod_extract.ys
Diffstat (limited to 'tests/various/submod_extract.ys')
| -rw-r--r-- | tests/various/submod_extract.ys | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/various/submod_extract.ys b/tests/various/submod_extract.ys new file mode 100644 index 000000000..8d11c21d3 --- /dev/null +++ b/tests/various/submod_extract.ys @@ -0,0 +1,21 @@ +read_verilog << EOT + module test(input [7:0] a, b, c, d, output [7:0] x, y, z); + assign x = a + b, y = b + c, z = c + d; + endmodule +EOT + +copy test gold +rename test gate + +submod -name mycell gate/x %ci* +design -copy-to mymap mycell +extract -map %mymap gate + +select -assert-count 3 gold/t:* +select -assert-count 3 gold/t:$add + +select -assert-count 3 gate/t:* +select -assert-count 3 gate/t:mycell + +miter -equiv -flatten gold gate miter +sat -verify -prove trigger 0 miter |