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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 16:18:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 16:18:07 -0700 |
| commit | 66607845eccb2e3bc17b017c4f6b109aeaecdf77 (patch) | |
| tree | 8f5ad0326afe17dc18ab79e16109d77d64fba165 /tests/various/shregmap.ys | |
| parent | 53fed4f7e9cd6512762cf93c74464d8e40efb414 (diff) | |
| download | yosys-66607845eccb2e3bc17b017c4f6b109aeaecdf77.tar.gz yosys-66607845eccb2e3bc17b017c4f6b109aeaecdf77.tar.bz2 yosys-66607845eccb2e3bc17b017c4f6b109aeaecdf77.zip | |
Remove Xilinx test
Diffstat (limited to 'tests/various/shregmap.ys')
| -rw-r--r-- | tests/various/shregmap.ys | 34 |
1 files changed, 0 insertions, 34 deletions
diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys index a717c54f1..16e5f40e1 100644 --- a/tests/various/shregmap.ys +++ b/tests/various/shregmap.ys @@ -31,37 +31,3 @@ sat -verify -prove-asserts -show-ports -seq 5 miter #design -load gate #stat - -########## - -design -load read -design -copy-to model $__XILINX_SHREG_ -hierarchy -top shregmap_variable_test -prep -design -save gold - -simplemap t:$dff t:$dffe -shregmap -tech xilinx - -#stat -# show -width -# write_verilog -noexpr -norename -select -assert-count 1 t:$_DFF_P_ -select -assert-count 2 t:$__XILINX_SHREG_ - -design -stash gate - -design -import gold -as gold -design -import gate -as gate -design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ -prep - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports -seq 5 miter - -# design -load gold -# stat - -# design -load gate -# stat - |