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| author | Zachary Snow <zach@zachjs.com> | 2021-02-05 19:38:10 -0500 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2021-02-05 19:51:30 -0500 |
| commit | 4b2f97733104c4e68dfdb0d89c1b03da137010c4 (patch) | |
| tree | 6f79a19d87ca4e717bf171b9183884f0c3d0682f /tests/various/port_sign_extend.ys | |
| parent | 3d9898272a5afd60f6080603bf065056d9dca000 (diff) | |
| download | yosys-4b2f97733104c4e68dfdb0d89c1b03da137010c4.tar.gz yosys-4b2f97733104c4e68dfdb0d89c1b03da137010c4.tar.bz2 yosys-4b2f97733104c4e68dfdb0d89c1b03da137010c4.zip | |
genrtlil: fix signed port connection codegen failures
This fixes binding signed memory reads, signed unary expressions, and
signed complex SigSpecs to ports. This also sets `is_signed` for wires
generated from signed params when -pwires is used. Though not necessary
for any of the current usages, `is_signed` is now appropriately set when
the `extendWidth` helper is used.
Diffstat (limited to 'tests/various/port_sign_extend.ys')
| -rw-r--r-- | tests/various/port_sign_extend.ys | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/tests/various/port_sign_extend.ys b/tests/various/port_sign_extend.ys index 0a6a93810..6d1adf7f3 100644 --- a/tests/various/port_sign_extend.ys +++ b/tests/various/port_sign_extend.ys @@ -1,22 +1,29 @@ -read_verilog port_sign_extend.v +read_verilog -nomem2reg port_sign_extend.v hierarchy flatten +proc +memory equiv_make ref act equiv equiv_simple equiv_status -assert delete -read_verilog port_sign_extend.v +read_verilog -nomem2reg port_sign_extend.v flatten +proc +memory equiv_make ref act equiv equiv_simple equiv_status -assert delete -read_verilog port_sign_extend.v +read_verilog -nomem2reg port_sign_extend.v hierarchy +proc +memory equiv_make ref act equiv prep -flatten -top equiv +equiv_induct equiv_status -assert |