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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 15:35:15 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 15:35:15 -0700 |
| commit | b959bf79c004fdf81ccc397d5aa774b67a09d6da (patch) | |
| tree | 16020f9dec76cf1e523509f837d3cfd23d2ff008 /tests/various/muxpack.v | |
| parent | ba52d9b4716b287b0a469597b748f9859e897329 (diff) | |
| download | yosys-b959bf79c004fdf81ccc397d5aa774b67a09d6da.tar.gz yosys-b959bf79c004fdf81ccc397d5aa774b67a09d6da.tar.bz2 yosys-b959bf79c004fdf81ccc397d5aa774b67a09d6da.zip | |
Add nonexcl case test, comment out two others
Diffstat (limited to 'tests/various/muxpack.v')
| -rw-r--r-- | tests/various/muxpack.v | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index d45ce4045..3a1086dbf 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -179,3 +179,21 @@ module cliffordwolf_freduce ( if (s == 2) o = d; end endmodule + +module case_nonexclusive_select ( + input wire [1:0] x, y, + input wire a, b, c, d, e, + output reg o +); + always @* begin + case (x) + 0, 2: o = b; + 1: o = c; + default: begin + o = a; + if (y == 0) o = d; + if (y == 1) o = e; + end + endcase + end +endmodule |