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authorEddie Hung <eddie@fpgeh.com>2019-04-11 15:03:40 -0700
committerEddie Hung <eddie@fpgeh.com>2019-04-11 15:03:40 -0700
commit7685469ee2f7bc038c4fd6fe98f93eb08d6fac7c (patch)
tree805b7ddc2ec354f091aa66d44e50c49be32f74f2 /tests/various/muxcover.ys
parentadc6efb58468a7e2f85f756d4a9d4686ad0a8c45 (diff)
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Add default entry to testcase
Diffstat (limited to 'tests/various/muxcover.ys')
-rw-r--r--tests/various/muxcover.ys5
1 files changed, 3 insertions, 2 deletions
diff --git a/tests/various/muxcover.ys b/tests/various/muxcover.ys
index 7ac460f13..594e62af6 100644
--- a/tests/various/muxcover.ys
+++ b/tests/various/muxcover.ys
@@ -8,12 +8,13 @@ read_verilog -formal <<EOT
3'b?1?: Y = B;
3'b1??: Y = C;
3'b000: Y = D;
+ default: Y = 'bx;
endcase
endmodule
EOT
-## Examle usage for "pmuxtree" and "muxcover"
+## Example usage for "pmuxtree" and "muxcover"
proc
pmuxtree
@@ -35,7 +36,7 @@ read_verilog -formal <<EOT
3'b010: Y = B;
3'b100: Y = C;
3'b000: Y = D;
- default: Y = 'bx;
+ default: Y = 'bx;
endcase
endmodule
EOT