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authorClaire Xen <claire@symbioticeda.com>2020-11-25 09:44:23 +0100
committerGitHub <noreply@github.com>2020-11-25 09:44:23 +0100
commitcf67e6a3977410e039d62a1e9f6c49c42cb97b08 (patch)
tree66475213fd27ac129f8a03eabf6131aae69730ba /tests/various/dynamic_part_select/multiple_blocking_gate.v
parentc6b5b18a30278637dcea4f9867631540b818716c (diff)
parentd68a8f9e2b20d9c4120a69e1a632a2d86250be86 (diff)
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Merge pull request #2133 from dh73/nodev_head
Adding latch tests for shift&mask AST dynamic part-select enhancements
Diffstat (limited to 'tests/various/dynamic_part_select/multiple_blocking_gate.v')
-rw-r--r--tests/various/dynamic_part_select/multiple_blocking_gate.v9
1 files changed, 5 insertions, 4 deletions
diff --git a/tests/various/dynamic_part_select/multiple_blocking_gate.v b/tests/various/dynamic_part_select/multiple_blocking_gate.v
index 073b559dc..840918876 100644
--- a/tests/various/dynamic_part_select/multiple_blocking_gate.v
+++ b/tests/various/dynamic_part_select/multiple_blocking_gate.v
@@ -1,8 +1,9 @@
+`default_nettype none
module multiple_blocking_gate (clk, ctrl, din, sel, dout);
- input clk;
- input [4:0] ctrl;
- input [1:0] din;
- input [0:0] sel;
+ input wire clk;
+ input wire [4:0] ctrl;
+ input wire [1:0] din;
+ input wire [0:0] sel;
output reg [31:0] dout;
reg [5:0] a;
reg [0:0] b;