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authorStefan Biereigel <stefan@biereigel.de>2020-02-03 21:29:54 +0100
committerStefan Biereigel <stefan@biereigel.de>2020-02-03 21:29:54 +0100
commit90c78f1f85f7e519b3d99a71722bbb40e7ee2960 (patch)
tree5dc3b99fb07dee98093fbfb49727a28c101fc34b /tests/various/bug1614.ys
parentb844b078db0c8b61758c562fbb8324bd5013bfa1 (diff)
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add testcase for #1614
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+read_verilog <<EOT
+module testcase;
+ wire [3:0] #1 a = 4'b0000;
+endmodule
+EOT