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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 11:05:36 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 11:05:36 -0700 |
| commit | ebe29b66593414d0317879359d1f1d1f61a9ecc4 (patch) | |
| tree | afcc4b47234b312bf52e58e2f5662dfaed392fca /tests/tools | |
| parent | 1b113a05742377f5b18d52bc5bf50b1991e88c19 (diff) | |
| download | yosys-ebe29b66593414d0317879359d1f1d1f61a9ecc4.tar.gz yosys-ebe29b66593414d0317879359d1f1d1f61a9ecc4.tar.bz2 yosys-ebe29b66593414d0317879359d1f1d1f61a9ecc4.zip | |
Use ABC to convert AIGER to Verilog, then sat against Yosys
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