Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc

4 files changed, 231 insertions, 12 deletions

diff --git a/tests/tools/autotest.mk b/tests/tools/autotest.mk
new file mode 100644
index 000000000..f65002cef
--- /dev/null
+++ b/tests/tools/autotest.mk
@@ -0,0 +1,8 @@
+
+EXTRA_FLAGS=
+
+$(MAKECMDGOALS):
+	@$(basename $(MAKEFILE_LIST)).sh -G -j $(EXTRA_FLAGS) $@
+
+.PHONY: $(MAKECMDGOALS)
+
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 7bccd9a5a..50f5cb580 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -6,38 +6,52 @@ use_xsim=false
 use_modelsim=false
 verbose=false
 keeprunning=false
+makejmode=false
+frontend="verilog"
 backend_opts="-noattr -noexpr"
+autotb_opts=""
 scriptfiles=""
 scriptopt=""
 toolsdir="$(cd $(dirname $0); pwd)"
+warn_iverilog_git=false
 
 if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then
 	( set -ex;  gcc -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
 fi
 
-while getopts xml:wkvrs:p: opt; do
+while getopts xmGl:wkjvref:s:p:n: opt; do
 	case "$opt" in
 		x)
 			use_xsim=true ;;
 		m)
 			use_modelsim=true ;;
+		G)
+			warn_iverilog_git=true ;;
 		l)
 			libs="$libs $(cd $(dirname $OPTARG); pwd)/$(basename $OPTARG)";;
 		w)
 			genvcd=true ;;
 		k)
 			keeprunning=true ;;
+		j)
+			makejmode=true ;;
 		v)
 			verbose=true ;;
 		r)
 			backend_opts="$backend_opts -norename" ;;
+		e)
+			backend_opts="$( echo " $backend_opts " | sed 's, -noexpr ,,; s,^ ,,; s, $,,;'; )" ;;
+		f)
+			frontend="$OPTARG" ;;
 		s)
 			[[ "$OPTARG" == /* ]] || OPTARG="$PWD/$OPTARG"
 			scriptfiles="$scriptfiles $OPTARG" ;;
 		p)
 			scriptopt="$OPTARG" ;;
+		n)
+			autotb_opts="$autotb_opts -n $OPTARG" ;;
 		*)
-			echo "Usage: $0 [-x|-m] [-w] [-k] [-v] [-r] [-l libs] [-s script] [-p cmdstring] verilog-files\n" >&2
+			echo "Usage: $0 [-x|-m] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] verilog-files\n" >&2
 			exit 1
 	esac
 done
@@ -77,17 +91,26 @@ do
 		exit 1
 	fi
 	[[ "$bn" == *_tb ]] && continue
-	echo -n "Test: $bn "
 
-	rm -f ${bn}.{err,log}
+	if $makejmode; then
+		status_prefix="Test: $bn "
+	else
+		status_prefix=""
+		echo -n "Test: $bn "
+	fi
+
+	rm -f ${bn}.{err,log,sikp}
 	mkdir -p ${bn}.out
 	rm -rf ${bn}.out/*
 
 	body() {
 		cd ${bn}.out
+		fn=$(basename $fn)
+		bn=$(basename $bn)
+
 		cp ../$fn $fn
 		if [ ! -f ../${bn}_tb.v ]; then
-			"$toolsdir"/../../yosys -b autotest -o ${bn}_tb.v $fn
+			"$toolsdir"/../../yosys -b "test_autotb $autotb_opts" -o ${bn}_tb.v $fn
 		else
 			cp ../${bn}_tb.v ${bn}_tb.v
 		fi
@@ -98,7 +121,7 @@ do
 
 		test_count=0
 		test_passes() {
-			"$toolsdir"/../../yosys -b "verilog $backend_opts" "$@" -o ${bn}_syn${test_count}.v $fn $scriptfiles
+			"$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@"
 			compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
 					${bn}_tb.v ${bn}_syn${test_count}.v $libs \
 					"$toolsdir"/../../techlibs/common/simlib.v \
@@ -108,13 +131,22 @@ do
 			test_count=$(( test_count + 1 ))
 		}
 
+		if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP $fn; then
+			touch ../${bn}.skip
+			return
+		fi
+
 		if [ -n "$scriptfiles" ]; then
-			test_passes
+			test_passes $fn $scriptfiles
 		elif [ -n "$scriptopt" ]; then
-			test_passes -p "$scriptopt"
+			test_passes -f "$frontend" -p "$scriptopt" $fn
+		elif [ "$frontend" = "verific" ]; then
+			test_passes -p "verific -vlog2k $fn; verific -import -all; opt; memory;;"
+		elif [ "$frontend" = "verific_gates" ]; then
+			test_passes -p "verific -vlog2k $fn; verific -import -gates -all; opt; memory;;"
 		else
-			test_passes -p "hierarchy; proc; opt; memory; opt; fsm; opt"
-			test_passes -p "hierarchy; proc; opt; memory; opt; fsm; opt; techmap; opt; abc -dff; opt"
+			test_passes -f "$frontend" -p "hierarchy; proc; opt; memory; opt; fsm; opt -fine" $fn
+			test_passes -f "$frontend" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" $fn
 		fi
 		touch ../${bn}.log
 	}
@@ -129,8 +161,17 @@ do
 
 	if [ -f ${bn}.log ]; then
 		mv ${bn}.err ${bn}.log
-		echo "-> ok"
-	else echo "-> ERROR!"; $keeprunning || exit 1; fi
+		echo "${status_prefix}-> ok"
+	elif [ -f ${bn}.skip ]; then
+		mv ${bn}.err ${bn}.skip
+		echo "${status_prefix}-> skip"
+	else
+		echo "${status_prefix}-> ERROR!"
+		if $warn_iverilog_git; then
+			echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of icarus verilog."
+		fi
+		$keeprunning || exit 1
+	fi
 done
 
 exit 0
diff --git a/tests/tools/txt2tikztiming.py b/tests/tools/txt2tikztiming.py
new file mode 100755
index 000000000..cfefe339f
--- /dev/null
+++ b/tests/tools/txt2tikztiming.py
@@ -0,0 +1,109 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+
+import argparse
+import fileinput
+import sys
+
+parser = argparse.ArgumentParser(description='Convert vcd2txt output to tikz-timing line.')
+parser.add_argument('filename', metavar='FILE', help='input txt file')
+parser.add_argument('signame', metavar='SIG', help='Signal name')
+parser.add_argument('-s', metavar='scale', default=1.0, type=float, help='Scale all time spans with this factor')
+parser.add_argument('-l', action='store_true', help='Logic signal (high/low)')
+parser.add_argument('-b', action='store_true', help='Display binary value')
+parser.add_argument('-x', action='store_true', help='Display hex value')
+parser.add_argument('-d', action='store_true', help='Display decimal value')
+args = parser.parse_args()
+
+start_time = None
+stop_time = None
+time_val = { }
+
+def value_to_logic(value):
+    found_x = False
+    for char in value:
+        if char == '1':
+            return "H"
+        if char == 'x':
+            found_x = True
+    return "U" if found_x else "L"
+
+def value_to_binary(value):
+    return "D{%s}" % value
+
+def value_to_hex(value):
+    hex_string = ""
+    found_def = False
+    while len(value) % 4 != 0:
+        value = "0" + value
+    while len(value) != 0:
+        bin_digits = value[0:4]
+        hex_digit = 0
+        value = value[4:]
+        for b in bin_digits:
+            if b == '0':
+                hex_digit = hex_digit * 2
+            elif b == '1':
+                hex_digit = hex_digit * 2 + 1
+            else:
+                hex_digit += 100
+        if hex_digit > 15:
+            hex_string += "x"
+        else:
+            found_def = True
+            hex_string += "0123456789abcdef"[hex_digit]
+    if not found_def:
+        return "U";
+    return "D{%s}" % hex_string
+
+def value_to_decimal(value):
+    val = 0
+    found_def = False
+    found_undef = False
+    for digit in value:
+        if digit == 'x':
+            found_undef = True
+        else:
+            val = val*2 + int(digit)
+            found_def = True
+    if found_def:
+        if found_undef:
+            return "D{X}"
+        else:
+            return "D{%d}" % val
+    return "U"
+
+for line in fileinput.input(args.filename):
+    (node, time, name, value) = line.strip().split('\t')
+    time = int(time)
+    if start_time is None or start_time > time:
+        start_time = time
+    if stop_time is None or stop_time < time:
+        stop_time = time
+    if name == args.signame:
+        if args.l:
+            time_val[+time] = value_to_logic(value)
+        elif args.b:
+            time_val[+time] = value_to_binary(value)
+        elif args.x:
+            time_val[+time] = value_to_hex(value)
+        elif args.d:
+            time_val[+time] = value_to_decimal(value)
+        else:
+            time_val[+time] = value
+
+if start_time not in time_val:
+    time_val[start_time] = "S"
+
+last_time = None
+last_value = None
+for t in sorted(time_val.keys()):
+    if last_time is not None:
+        print("%f%s" % ((t - last_time)*args.s, last_value), end='')
+    (last_time, last_value) = (t, time_val[t])
+if last_time < stop_time:
+    print("%f%s" % ((stop_time - last_time)*args.s, last_value), end='')
+print('')
+
diff --git a/tests/tools/vcd2txt.pl b/tests/tools/vcd2txt.pl
new file mode 100755
index 000000000..92d3d1652
--- /dev/null
+++ b/tests/tools/vcd2txt.pl
@@ -0,0 +1,61 @@
+#!/usr/bin/perl -w
+#
+# Note: You might need to install the Verilog::VCD package using CPAN..
+
+use strict;
+use Data::Dumper;
+use Verilog::VCD qw(parse_vcd list_sigs);
+
+$| = 1;
+
+my $from_time = -1;
+my $to_time = -1;
+
+while (1)
+{
+	if ($ARGV[0] eq '-f') {
+		$from_time = +$ARGV[1];
+		shift @ARGV;
+		shift @ARGV;
+		next;
+	}
+	if ($ARGV[0] eq '-t') {
+		$to_time = +$ARGV[1];
+		shift @ARGV;
+		shift @ARGV;
+		next;
+	}
+	last;
+}
+
+if ($#ARGV < 0) {
+	print STDERR "\n";
+	print STDERR "VCD2TXT - Convert VCD to tab-separated text file\n";
+	print STDERR "\n";
+	print STDERR "Usage: $0 [-f from_time] [-t to_time] input.vcd [<signal regex> ...]\n";
+	print STDERR "\n";
+	exit 1;
+}
+
+my $vcd = parse_vcd($ARGV[0]);
+
+for my $node (keys $vcd) {
+	for my $net (@{$vcd->{$node}->{'nets'}}) {
+		my $dump_this = $#ARGV == 0;
+		for (my $i = 1; $i <= $#ARGV; $i++) {
+			my $regex = $ARGV[$i];
+			$dump_this = 1 if ($net->{"hier"} . "." . $net->{"name"}) =~ /$regex/;
+		}
+		next unless $dump_this;
+		my $cached_value = "";
+		for my $tv (@{$vcd->{$node}->{'tv'}}) {
+			$cached_value = $tv->[1], next if $from_time >= 0 and +$tv->[0] < $from_time;
+			next if $to_time >= 0 and +$tv->[0] > $to_time;
+			printf "%s\t%s\t%s\t%s\n", $node, $from_time, $net->{"hier"} . "." . $net->{"name"}, $cached_value
+					if $cached_value ne "" and $from_time >= 0 and +$tv->[0] > $from_time;
+			printf "%s\t%s\t%s\t%s\n", $node, $tv->[0], $net->{"hier"} . "." . $net->{"name"}, $tv->[1];
+			$cached_value = "";
+		}
+	}
+}
+