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| author | Claire Xen <claire@clairexen.net> | 2021-12-10 11:23:53 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-12-10 11:23:53 +0100 |
| commit | ce82afe44f4c396c253a293a5f0d56212fe27010 (patch) | |
| tree | ce3d60c7aa65c8f67a583f1d8da1913ade20fd9e /tests/techmap | |
| parent | cdb57118758f855518ad416d12728d72bff58c10 (diff) | |
| parent | d6e4d3f1ba9191f0f3bbed2d47a9ef80b8614e77 (diff) | |
| download | yosys-ce82afe44f4c396c253a293a5f0d56212fe27010.tar.gz yosys-ce82afe44f4c396c253a293a5f0d56212fe27010.tar.bz2 yosys-ce82afe44f4c396c253a293a5f0d56212fe27010.zip | |
Merge pull request #3099 from YosysHQ/claire/readargs
Use "read" command to parse HDL files from Yosys command-line
Diffstat (limited to 'tests/techmap')
| -rw-r--r-- | tests/techmap/mem_simple_4x1_runtest.sh | 2 | ||||
| -rw-r--r-- | tests/techmap/recursive_runtest.sh | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh index 9c41fa56a..b486de5c7 100644 --- a/tests/techmap/mem_simple_4x1_runtest.sh +++ b/tests/techmap/mem_simple_4x1_runtest.sh @@ -2,7 +2,7 @@ set -e -../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v +../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'read_verilog mem_simple_4x1_uut.v; proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v diff --git a/tests/techmap/recursive_runtest.sh b/tests/techmap/recursive_runtest.sh index 0725ccf40..564d678fa 100644 --- a/tests/techmap/recursive_runtest.sh +++ b/tests/techmap/recursive_runtest.sh @@ -1,3 +1,3 @@ set -e -../../yosys -p 'hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' recursive.v +../../yosys -p 'read_verilog recursive.v; hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' |